The overload behaviour of the receiver ADCs in the ADRV9008-1 and ADRV9009 devices appears to be quite erratic. The PFIR filter is able to be modified such that it will saturate before the ADC overloads, which seems to signify that the resultant output is caused by the ADC itself. The attached plots from the Talise gui show a large signal that is causing an overload, which rather than saturating, appears to drop back to around zero. Is there any further information available as to the handling of the bit growth through the various decimation filters following the ADC? is there more than 16 effective bits through the ADC and filter chain or are they limited to 16 bits through each filtering stage? Is there any way to change the ADC behaviour to saturate rather than the wrapping behaviour as is seen in the image below?
What is the input level that you are giving? Make sure that you are giving the input level within the datasheet specs otherwise the ADC will saturate.
SBosworth716 said:Is there any way to change the ADC behaviour to saturate rather than the wrapping behaviour as is seen in the image below?
No. Not possible. You will have to either decrease the gain or decrease the input level to prevent the ADC from saturating.
Hi Srimoyi, thanks for the reply, though i'm not sure you have understood our issue. I am aware that the input level that we are driving is beyond the limit of the ADC and as such the waveform will be distorted, this is not our typical operation level, rather just to illustrate the issue. In our application we require a fixed gain setting for a collection period and as such if a large signal is received during that period, it would be useful if the spectrum was not entirely splattered with signal products as a result of the ADC wrapping to zero behavior.
i understand that if we used AGC this would be less of an issue, but for our application gain step adjustments are only applied periodically, as the gain must be constant for the duration of data collection, hence my question re. the behaviour when clipping. If the overload behaviour was similar to typical ADC saturation (clamping at the maximum output level) this would be far more usable.
Are there any other options? Thanks
There are no option to change the behavior internally other than AGC. Not sure if external circuit like limiter is an option here.
You may need to use AGC with gain update interval set for the period you need. From User guide,
The AGC uses a gain update counter to time gain changes, with gain changes made when the counter expires. The counter value, and therefore the time spacing between possible gain changes, is user programmable through the agcGainUpdateCounter parameter