Multi-ADRV9009s sync problem

Hello,

I am using one zcu102+two adrv9009s.  According the UG1295 and suggestions in this zone, I used clock distribution as below. I used the ad9528 on the master adrv9009 to create 3 sysrefs(0.12MHz one is for the first adrv9009 and one is for the second adrv9009 and one is for fpga) and four dev_clks(245.76MHz)

I adjusted the phase difference within 1ns between sysrefs of the first and the second adrv9009.

To make the multichips sync, I follow the following steps.

In my power up and power down test, sometimes the two adrv9009 can be synced,like the figure below. the RX1 of the master adrv9009 and the RX1 of the slave adrv9009 were synced. 

But sometimes, the master adrv9009 was not synced with the slave adrv9009, showing that the RX1 of the master one were not synced with the RX1 of the slave one. but the I0 and Q0 of the same adrv9009 were synced.

The statup log message was below.

Hello
rx_clkgen: MMCM-PLL locked (245760000 Hz)
tx_clkgen: MMCM-PLL locked (122880000 Hz)
rx_os_clkgen: MMCM-PLL locked (122880000 Hz)
rx_adxcvr: OK (9830400 kHz)
tx_adxcvr: OK (4915200 kHz)
rx_os_adxcvr: OK (4915200 kHz)
talise: Device Revision 192, Firmware 6.0.2, API 3.6.0.21110623253299205
talise: Calibrations completed successfully
warning: TAL_FRAMER_A status 0x1
talise: Device Revision 192, Firmware 6.0.2, API 3.6.0.21110623253299205
talise: Calibrations completed successfully
rx_jesd: Lane 2 desynced (20 errors), restarting link
rx_jesd: Lane 3 desynced (11 errors), restarting link
rx_os_jesd: Lane 1 desynced (32 errors), restarting link
rx_os_jesd: Lane 2 desynced (7 errors), restarting link
rx_os_jesd: Lane 3 desynced (10 errors), restarting link
rx_jesd status:
Link is enabled
Measured Link Clock: 245.772 MHz
Reported Link Clock: 245.760 MHz
Lane rate: 9830.400 MHz
Lane rate / 40: 245.760 MHz
LMFC rate: 7.680 MHz
Link status: DATA
SYSREF captured: Yes
SYSREF alignment error: No
tx_jesd status:
Link is enabled
Measured Link Clock: 122.887 MHz
Reported Link Clock: 122.880 MHz
Lane rate: 4915.200 MHz
Lane rate / 40: 122.880 MHz
LMFC rate: 7.680 MHz
SYNC~: deasserted
Link status: DATA
SYSREF captured: Yes
SYSREF alignment error: No
rx_os_jesd status:
Link is enabled
Measured Link Clock: 122.887 MHz
Reported Link Clock: 122.880 MHz
Lane rate: 4915.200 MHz
Lane rate / 40: 122.880 MHz
LMFC rate: 7.680 MHz
Link status: DATA
SYSREF captured: Yes
SYSREF alignment error: No
tx_dac: Successfully initialized (245773315 Hz)
rx_adc: Successfully initialized (245771789 Hz)

I checked the MCS state, from the log message, it did not show MCS error message and indeedly they were both 0x0B.  Coule you give me some suggestions? Thanks a lot.