Relation between DCLK and SYSREF of JESD204B for ADRV9009


Here are our clock calculations based on the baseband sampling rate,

Fs = 110.592MSPS

M=2; S=1; L=1; K=32; N=16;

Lane rate = 4423.68Mbps (Fs*N*M*10/(8*L))

LMFC = lane rate/(20*32) = 6.912MHz

SYSREF = Fs/LCM(64,20*32) = 172.8KHz

DCLK = lane rate/40 = 110.592MHz (even though the clock PLL in ADRV9009 is fractional one, to maintain the synchronization the even integer factor is selected. Here it is 40)

Let me know your inputs on the above calculations. Is it possible to generate DCLK of 110.592MHz from AD9528?