Is the reference clock of ADRV9009 from the clock generator (DCLK of AD9528 or any other JESD clock generator) should be in the value of 122.88, 184.32 or 245.76?(from the table 41 of UG-1295)
Aren't we allowed to generate any other frequencies which would be the even integer multiple of SYSREF( DCLK = 2N*SYSREF)?
The SYSREF is dependent on Fs which in turn dependent on the baseband signal's characteristics.
In evaluation board there is a 122.88 MHz crystal which restricts Device clock to few frequencies. Same as AD9371 eval board.
In Profile generator tool , if you change 122.88 VCXO value , you can generate required device clock.
So, we need to select VCXO based on our JESD requirements.
And there isn't any restriction from ADRV9009 regarding reference clock values, right?
The chip can accept reference clock between 10MHz and 1000 MHz.