Dear all, I need to synchronize several ADRV9009.
I just have found that the function TALISE_enableMultichipRfLOPhaseSync exists: it is not mentioned in UG-1295 (6/2018—Revision 0: Initial Version), nor present in the example code provided.
I just found https://ez.analog.com/wide-band-rf-transceivers/tes-gui-software-support-adrv9009-adrv9008-1-adrv9008-2/f/q-a/115831/adrv9009-mcs-and-rf-pll-phase-sync-question as I was searching for help on TALISE_enableMultichipSync.
What is the exact sequence of calls for both functions? it is not clear in the above discussion!
Without enableMultichipRfLOPhaseSync, I achieved to have mcsStatus equals 0xB, but as soon as I call enableMultichipRfLOPhaseSync, mcsStatus is zero.
Is the sequence in https://ez.analog.com/wide-band-rf-transceivers/design-support-adrv9008-1-adrv9008-2-adrv9009/f/q-a/115291/adrv9009-phase-sync the correct one?
Ref: talise: Device Revision 192, Firmware 6.0.2, API 184.108.40.206
It seems that in the last days the issue was related to the configuration of de AD9528 PLL.We used the SYSREF_REQ pin, so the SYSREF pulse was "generated internally" and resampled by a 122.88 MHz clock…
Followed further in the below post:
Yes.You can follow the sequence.
Thank you for your answer. Nevertheless, I did not manage to get any better result. I can give some details:
From a situation where mcsStatus equals 0xB (returned by TALISE_enableMultichipSync(&talDev, 0, &mcsStatus);) :
If I call TALISE_enableMultichipRfLOPhaseSync(&talDev, 1); I get mcsStatus to zero, then after some SYSREF pulses mcsStatus is 0x8.
Then if I call TALISE_enableMultichipRfLOPhaseSync(&talDev, 0); I get mcsStatus to zero again, and after some SYSREF pulses mcsStatus is 0x3.
I never get 0xB again, except if I call TALISE_enableMultichipSync(&talDev, 1, ...) and send some SYSREF pulses again.
I have never seen bit 2 of mcsStatus active (0x4). On some other discussion I read that it was right to get 0x3 after PhaseSync, but I would expect to get 0xF.
I have two ADRV9009 that receive the same REFCLK, and SYSREF pulses. I can watch the RF output of both boards on the scope, the phase difference is (temporarily) constant, but random after each power up.
I have tried many different startup sequences. I have never seen the phase being slowly "corrected".
Is there restrictions on the period of the SYSREF pulses ?
Please refer below screenshot from help file for the sequence for running the RF PLL phase sync on ADRV9009.
Please refer below ezone post for additional information,
I would like to have a single initialization sequence, not two sequences that I have to merge in some way. My current code is based on the "headless.c" file provided by TES. Where exactly do I have to insert the calls to TALISE_enableMultichipRfLOPhaseSync in this initialization code? Everything I tried so far failed. Do I have to change the order of initialization significantly? Can we imagine that some day the TES will produce a code with TALISE_enableMultichipRfLOPhaseSync (possibly in a comment)?
What do you thing of the values I mentioned 4 days ago? (0xB, 0x3, 0x8). Is it right to expect 0xF?
In the mean time somebody points me a demo board with two ADRV9009:
What is the initialization code of this board?
Please post in FPGA Reference design forum for queries related to Fmcomms8.
For details on Two ADRV9009 please refer below link,
For PLL Phase sync, Please follow the below sequence.
1) Change the rfpllphasesync mode to init and track
2) Insert the below new MCS sequence in the device initialization sequence explained in UG.