ADRV9009 MCS and RF PLL Phase Sync Question

Hello,

    I am using custom board with ultrascale+ and muti adrv9009.

    I need to use MCS and RF PLL phase sync function.

    The software that I use is no-os example( I modified for muti chip) and Firmware is 6.0.2, API is 3.6.0.5.
   

    Refer to UG1295 and API manual,  I did some tests and got results as list:

    1. Just run TALISE_enableMultichipSync(), and .rfPllPhaseSyncMode = TAL_RFPLLMCS_INIT_AND_SYNC.

        Result : After TALISE_enableMultichipSync, I get MultiChipSyncStatus,the SyncStatus value is 0xB. Look muti TX Singal on the oscilloscope, RF PLL Phase Sync is not sync.

    2. Run TALISE_enableMultichipSync(), and set .rfPllPhaseSyncMode = TAL_RFPLLMCS_INIT_AND_SYNC.

        Result : same as test 1.

    3. Just run TALISE_enableMultichipRfLOPhaseSync(), and set .rfPllPhaseSyncMode = TAL_RFPLLMCS_INIT_AND_SYNC.

        Result : After TALISE_enableMultichipSync, I get MultiChipSyncStatus,the SyncStatus value is 0x3, JESD Link Status error.

    3.Set .rfPllPhaseSyncMode = TAL_RFPLLMCS_INIT_AND_SYNC, run TALISE_enableMultichipSync() first, then run TALISE_enableMultichipRfLOPhaseSync() , and set                          .rfPllPhaseSyncMode = TAL_RFPLLMCS_INIT_AND_SYNC.

        Result : After TALISE_enableMultichipSync, I get MultiChipSyncStatus,the SyncStatus value is 0xB, after TALISE_enableMultichipRfLOPhaseSync() , the SyncStatus value is 0x3, JESD Link Status OK, RF PLL Phase is synced.

So,

1. Should I use both TALISE_enableMultichipSync() and TALISE_enableMultichipRfLOPhaseSync() for mcs and RF PLL sync?

2. why does TALISE_enableMultichipRfLOPhaseSync() reset  Device Clock divider Sync Status? Does this have any effect to msc ?

  • 0
    •  Analog Employees 
    on Sep 5, 2019 10:17 AM over 1 year ago
    Should I use both TALISE_enableMultichipSync() and TALISE_enableMultichipRfLOPhaseSync() for mcs and RF PLL sync?

    Yes. Your third sequence is correct. You have to first run MCS to set JESD204B deterministic latency using SYSREF signal pulses as normal. Then you have to run RFPLL phase synchronization that uses existing signaling and the SYSREF signal to accomplish LO phase synchronization.

    Hope you are sending the SYSREF's after the MCS as per the JES204B API Initialization sequence given in UG.

  • Hi,srimoyi.

         I use thrid sequence now, and all chip' configuration is same.

         But I find the baseband data received between channels may differ by one LMFC period time. Some channel's data may differ by one sampling point. It measn one channel may delay ~130ns to others in 245.76MHz rx data rate. Each chip's RX1 signal screen shot as flow:

    RX Data Wave

         In addition, the delay relationship between each channel will change after each power-on, but it is a fixed difference of one LMFC period.

         Is that normanal? I think it has some error in configurations, one sampling point can calibrate through baseband data, but 130 ns delay can not calibrate through user's baseband data that with more than ~7.7MHz frequency.

         Could you please give me some suggestion? Thanks.

  • 0
    •  Analog Employees 
    on Sep 9, 2019 7:00 AM over 1 year ago in reply to l312361206

    In order to rule out configuration issue, can you try running RFPLL MCS using TES GUI and then check the phase difference at the output of RX channels?

    Does the relative phase difference between the channels remains constant with every power-up? MCS will only make sure that the relative phase difference between channels remains constant with every power-up. The absolute phase needs to calibrated externally.

  • Thanks for your reply!

    But Sorry, my custom board didn't have Ethernet port ,so I can't use TES GUI for online Configurating. But my talise_config.c file is generated by TES GUI.

    I am sure that the relative phase will change between channels with every power-up.

    I wonder if some adrv9009 channel's JESD FIFO is full or empty ? or the time of data push to FIFO is not sync. I want to reset the FIFO, but I did not find the way.

  • 0
    •  Analog Employees 
    on Sep 9, 2019 9:44 AM over 1 year ago in reply to l312361206

    Refer to the below figure from UG. At each power-up, the phase of the transmitter output compared to the signal generator reference is a random value on each of the five power cycles. MCS brings the initial random phase to a repeatable value.

    So, after RFPLL MCS, the relative phase difference should remain constant after each power-up. Hope you are connecting the same reference clock to all the boards. Change the RFPLL phase sync mode to init and track continuously and then check if the phase difference between channels is settling to a constant value after each power-up.

    You can reset the FIFO by disabling and enabling the deframer link using this API:

    EnableDeframerLink()