Error "ARM Profile error during bootup" on ZCU102 + ADRV9009

Hello,

I got errors of ARM profile error during bootup. The log is as follows:

  6.436709] adrv9009 spi1.1: ERROR: 3: TALISE_loadArmFromBinary(): ARM Profile error during bootup
[    6.445600] adrv9009 spi1.1: adrv9009_setup:497 (ret 5)
[    8.551924] adrv9009 spi1.1: ERROR: 177: ARM Mailbox Busy. Command not executed in TALISE_sendArmCommand()
[   10.662349] adrv9009 spi1.1: ERROR: 177: ARM Mailbox Busy. Command not executed in TALISE_sendArmCommand()
[   12.773011] adrv9009 spi1.1: ERROR: 177: ARM Mailbox Busy. Command not executed in TALISE_sendArmCommand()
[   12.782599] adrv9009 spi1.1: adrv9009_setup:525 (ret 5)
[   12.787878] adrv9009 spi1.1: adrv9009_setup:531 (ret 0)
[   14.893930] adrv9009 spi1.1: ERROR: 177: ARM Mailbox Busy. Command not executed in TALISE_sendArmCommand()
[   14.903517] adrv9009 spi1.1: adrv9009_setup:541 (ret 5)
[   15.111449] adrv9009 spi1.1: ERROR: 178: Device not in radioOff/IDLE state. Error in TALISE_enableTrackingCals()
[   15.121554] adrv9009 spi1.1: adrv9009_setup:707 (ret 5)
[   15.126885] adrv9009 spi1.1: ERROR: 153: device->rx->rxAgcCtrl->agcGainUpdateTime_us out of range in TALISE_setupRxAgc()
[   15.137682] adrv9009 spi1.1: adrv9009_setup:711 (ret 9)
[   17.243789] adrv9009 spi1.1: ERROR: 177: ARM Mailbox Busy. Command not executed in TALISE_sendArmCommand()
[   17.253376] adrv9009 spi1.1: adrv9009_setup:717 (ret 5)
[   17.260951] adrv9009 spi1.1: ERROR: 246: ARM binary must be loaded before calling TALISE_getArmVersion_v2()
[   17.270658] adrv9009 spi1.1: adrv9009_probe: adrv9009 Rev 192, Firmware 0.0.0 API version: 3.4.0.0 successfully initialized
[   17.282464] PLL: enable

 I exported the profile of ADRV9009 from TES with the configuration of JESD204B as below:

- IQ sample 307.2 Msps

- Bandwidth = 100 MHz

- device clock = 153.6 MHz

The detail configuration is embedded below in talise_config.c.

I imported the parameters from configured file into my own device tree (adi-adrv9009_hpc1.dtsi), and getting above errors.

Could you help me to identify the cause of errors? How to overcome it?

Another question: As in the document of ADRV9009 (page 106 - UG-1295), the valid range of clkPllVcoFreq_kHz is "6,000,000 to 12,000,000". However, the parameters which is exported by TES is 12,288,000. Is there anything wrong?

/**
 * \file talise_config.c
 * \brief Contains Talise configuration settings for the Talise API
 *
 * Copyright 2015-2017 Analog Devices Inc.
 * Released under the AD9378-AD9379 API license, for more information see the "LICENSE.txt" file in this zip file.
 *
 * The top level structure taliseDevice_t talDevice uses keyword
 * extern to allow the application layer main() to have visibility
 * to these settings.
 *
 * This file may not be fully complete for the end user application and 
 * may need to updated for AGC, GPIO, and DAC full scale settings. 
 * To create a full initialisation routine, the user should also refer to the 
 * Iron Python initialisation routine generated by the GUI, and also the Talise User Guide.
 *
 */

#include "talise_types.h"
#include "talise_config.h"
#include "talise_error.h"
#include "talise_agc.h"
#ifdef ADI_ZYNQ_PLATFORM
#include "zynq_platform.h"
#endif

int16_t txFirCoefs[20] = {-15, 22, -41, 83, -145, 259, -518, 1199, -2619, 19936, -2619, 1199, -518, 259, -145, 83, -41, 22, -15, 0};

int16_t rxFirCoefs[48] = {-1, 0, 4, 1, -16, -6, 49, 23, -124, -67, 274, 168, -542, -378, 985, 784, -1689, -1553, 2805, 3067, -4859, -7088, 9643, 31289, 31289, 9643, -7088, -4859, 3067, 2805, -1553, -1689, 784, 985, -378, -542, 168, 274, -67, -124, 23, 49, -6, -16, 1, 4, 0, -1};

int16_t obsrxFirCoefs[24] = {32, -15, 19, -22, 20, -17, -21, 59, -163, 435, -1731, 19255, -1731, 435, -163, 59, -21, -17, 20, -22, 19, -15, 32, 0};

#ifdef ADI_ZYNQ_PLATFORM /** < Insert Customer Platform HAL State Container here>*/
/*
 * Platform Layer SPI settings - this structure is specific to ADI's platform layer code.
 * User should replace with their own structure or settings for their hardware
 */
zynqSpiSettings_t spiDev1 =
{
	.chipSelectIndex = 1,
	.writeBitPolarity = 0,
	.longInstructionWord = 1,
	.CPHA = 0,
	.CPOL = 0,
	.mode = 0,
	.spiClkFreq_Hz = 25000000
};

/*
 * Platform Layer settings - this structure is specific to ADI's platform layer code.
 * User should replace with their own structure or settings for their hardware
 * The structure is held in taliseDevice_t below as a void pointer, allowing
 * the customer to pass any information for their specific hardware down to the
 * hardware layer code.
 */
zynqAdiDev_t talDevHalInfo =
{
	.devIndex = 1,
	.spiSettings = &spiDev1,
	.spiErrCode = 0,
	.timerErrCode = 0,
	.gpioErrCode = 0,
	.logLevel = ADIHAL_LOG_ALL
};
#endif
/**
 *  TalDevice a structure used by the Talise API to hold the platform hardware
 *  structure information, as well as an internal Talise API state container
 *  (devStateInfo) of runtime information used by the API.
 **/
taliseDevice_t talDevice =
{
#ifdef ADI_ZYNQ_PLATFORM
    /* Void pointer of users platform HAL settings to pass to HAL layer calls
     * Talise API does not use the devHalInfo member */
	.devHalInfo = &talDevHalInfo,
#else
	.devHalInfo = NULL,     /*/** < Insert Customer Platform HAL State Container here>*/
#endif
	/* devStateInfo is maintained internal to the Talise API, just create the memory */
	.devStateInfo = {0}

};

taliseInit_t talInit =
{
	/* SPI settings */
    .spiSettings =
    {
		.MSBFirst            = 1,  /* 1 = MSBFirst, 0 = LSBFirst */
		.enSpiStreaming      = 0,  /* Not implemented in ADIs platform layer. SW feature to improve SPI throughput */
		.autoIncAddrUp       = 1,  /* Not implemented in ADIs platform layer. For SPI Streaming, set address increment direction. 1= next addr = addr+1, 0:addr=addr-1 */
		.fourWireMode        = 1,  /* 1: Use 4-wire SPI, 0: 3-wire SPI (SDIO pin is bidirectional). NOTE: ADI's FPGA platform always uses 4-wire mode */
		.cmosPadDrvStrength  = TAL_CMOSPAD_DRV_2X /* Drive strength of CMOS pads when used as outputs (SDIO, SDO, GP_INTERRUPT, GPIO 1, GPIO 0) */
	},
	
    /* Rx settings */
    .rx = 
    {
        .rxProfile =
        {
            .rxFir = 
            {
                .gain_dB = -6,                /* filter gain */
                .numFirCoefs = 48,            /* number of coefficients in the FIR filter */
                .coefs = &rxFirCoefs[0]
            },
            .rxFirDecimation = 2,            /* Rx FIR decimation (1,2,4) */
            .rxDec5Decimation = 4,            /* Decimation of Dec5 or Dec4 filter (5,4) */
            .rhb1Decimation = 1,            /* RX Half band 1 decimation (1 or 2) */
            .rxOutputRate_kHz = 153600,            /* Rx IQ data rate in kHz */
            .rfBandwidth_Hz = 100000000,    /* The Rx RF passband bandwidth for the profile */
            .rxBbf3dBCorner_kHz = 100000,    /* Rx BBF 3dB corner in kHz */
            .rxAdcProfile = {341, 221, 181, 90, 1280, 699, 1282, 58, 863, 21, 568, 27, 48, 31, 22, 201, 0, 0, 0, 0, 50, 0, 6, 4, 43, 0, 6, 4, 43, 0, 25, 3, 0, 0, 25, 3, 0, 0, 165, 44, 31, 905},            /* pointer to custom ADC profile */
            .rxDdcMode = TAL_RXDDC_BYPASS,   /* Rx DDC mode */
            .rxNcoShifterCfg =
            {
                .bandAInputBandWidth_kHz = 0,
                .bandAInputCenterFreq_kHz = 0,
                .bandANco1Freq_kHz = 0,
                .bandANco2Freq_kHz = 0,
                .bandBInputBandWidth_kHz = 0,
                .bandBInputCenterFreq_kHz = 0,
                .bandBNco1Freq_kHz = 0,
                .bandBNco2Freq_kHz = 0
            }
        },
        .framerSel = TAL_FRAMER_A,            /* Rx JESD204b framer configuration */
        .rxGainCtrl = 
        {
            .gainMode = TAL_MGC,            /* taliserxGainMode_t gainMode */
            .rx1GainIndex = 255,            /* uint8_t rx1GainIndex */
            .rx2GainIndex = 255,            /* uint8_t rx2GainIndex */
            .rx1MaxGainIndex = 255,            /* uint8_t rx1MaxGainIndex */
            .rx1MinGainIndex = 195,            /* uint8_t rx1MinGainIndex */
            .rx2MaxGainIndex = 255,            /* uint8_t rx2MaxGainIndex */
            .rx2MinGainIndex = 195            /* uint8_t rx2MinGainIndex */
        },
        .rxChannels = TAL_RX1RX2,                /* The desired Rx Channels to enable during initialization */
    },


    /* Tx settings */
    .tx = 
    {
        .txProfile =
        {
            .dacDiv = 1,                        /* The divider used to generate the DAC clock */
            .txFir = 
            {
                .gain_dB = 6,                        /* filter gain */
                .numFirCoefs = 20,                    /* number of coefficients in the FIR filter */
                .coefs = &txFirCoefs[0]
            },
            .txFirInterpolation = 1,                    /* The Tx digital FIR filter interpolation (1,2,4) */
            .thb1Interpolation = 2,                    /* Tx Halfband1 filter interpolation (1,2) */
            .thb2Interpolation = 2,                    /* Tx Halfband2 filter interpolation (1,2)*/
            .thb3Interpolation = 1,                    /* Tx Halfband3 filter interpolation (1,2)*/
            .txInt5Interpolation = 1,                    /* Tx Int5 filter interpolation (1,5) */
            .txInputRate_kHz = 307200,                    /* Primary Signal BW */
            .primarySigBandwidth_Hz = 100000000,    /* The Rx RF passband bandwidth for the profile */
            .rfBandwidth_Hz = 277000000,            /* The Tx RF passband bandwidth for the profile */
            .txDac3dBCorner_kHz = 277000,                /* The DAC filter 3dB corner in kHz */
            .txBbf3dBCorner_kHz = 138500,                /* The BBF 3dB corner in kHz */
            .loopBackAdcProfile = {283, 243, 181, 90, 1280, 1027, 1491, 276, 885, 66, 609, 15, 48, 30, 23, 214, 0, 0, 0, 0, 54, 0, 7, 5, 26, 0, 7, 5, 26, 0, 25, 3, 0, 0, 25, 3, 0, 0, 165, 44, 15, 905}
        },
        .deframerSel = TAL_DEFRAMER_A,                    /* Talise JESD204b deframer config for the Tx data path */
        .txChannels = TAL_TX1TX2,                            /* The desired Tx channels to enable during initialization */
        .txAttenStepSize = TAL_TXATTEN_0P05_DB,            /* Tx Attenuation step size */
        .tx1Atten_mdB = 0,                            /* Initial Tx1 Attenuation */
        .tx2Atten_mdB = 0,                            /* Initial Tx2 Attenuation */
        .disTxDataIfPllUnlock = TAL_TXDIS_TX_RAMP_DOWN_TO_ZERO    /* Options to disable the transmit data when the RFPLL unlocks. */
    },


    /* ObsRx settings */
    .obsRx = 
    {
        .orxProfile =
        {
            .rxFir = 
            {
                .gain_dB = 6,                /* filter gain */
                .numFirCoefs = 24,            /* number of coefficients in the FIR filter */
                .coefs = &obsrxFirCoefs[0]
            },
            .rxFirDecimation = 1,            /* Rx FIR decimation (1,2,4) */
            .rxDec5Decimation = 4,            /* Decimation of Dec5 or Dec4 filter (5,4) */
            .rhb1Decimation = 1,            /* RX Half band 1 decimation (1 or 2) */
            .orxOutputRate_kHz = 307200,            /* Rx IQ data rate in kHz */
            .rfBandwidth_Hz = 277000000,    /* The Rx RF passband bandwidth for the profile */
            .rxBbf3dBCorner_kHz = 138500,    /* Rx BBF 3dB corner in kHz */
            .orxLowPassAdcProfile = {259, 249, 181, 90, 1280, 1180, 1517, 306, 891, 81, 610, 10, 48, 30, 23, 215, 0, 0, 0, 0, 54, 0, 7, 5, 26, 0, 7, 5, 26, 0, 25, 3, 0, 0, 25, 3, 0, 0, 165, 44, 15, 905},
            .orxBandPassAdcProfile = {210, 131, 181, 90, 1280, 2828, 1423, 0, 694, 535, 610, 111, 1, 11, 18, 186, 0, 0, 0, 0, 47, 0, 7, 5, 26, 0, 7, 5, 26, 0, 25, 3, 0, 0, 25, 3, 0, 0, 165, 44, 15, 905},
            .orxDdcMode = TAL_ORXDDC_DISABLED,   /* ORx DDC mode */
            .orxMergeFilter  = {42, 326, -447, -124, 933, -774, -806, 2267, -1039, -3716, 9469, 20704}
        },
        .orxGainCtrl = 
        {
            .gainMode = TAL_MGC,
            .orx1GainIndex = 255,
            .orx2GainIndex = 255,
            .orx1MaxGainIndex = 255,
            .orx1MinGainIndex = 195,
            .orx2MaxGainIndex = 255,
            .orx2MinGainIndex = 195
        },
        .framerSel = TAL_FRAMER_B,                /* ObsRx JESD204b framer configuration */
        .obsRxChannelsEnable = TAL_ORX1,        /* The desired ObsRx Channels to enable during initialization */
        .obsRxLoSource = TAL_OBSLO_RF_PLL                /* The ORx mixers can use the TX_PLL */
    },

    /* Digital Clock Settings */
    .clocks = 
    {
        .deviceClock_kHz = 153600,            /* CLKPLL and device reference clock frequency in kHz */
        .clkPllVcoFreq_kHz = 12288000,        /* CLKPLL VCO frequency in kHz */
        .clkPllHsDiv = TAL_HSDIV_5,            /* CLKPLL high speed clock divider */
        .rfPllUseExternalLo = 0,                /* 1= Use external LO for RF PLL, 0 = use internal LO generation for RF PLL */
        .rfPllPhaseSyncMode = TAL_RFPLLMCS_INIT_AND_CONTTRACK                /* RFPLL MCS (Phase sync) mode */
    },

    /* JESD204B settings */
    .jesd204Settings = 
    {
        /* Framer A settings */
        .framerA = 
        {
            .bankId = 1,                    /* JESD204B Configuration Bank ID -extension to Device ID (Valid 0..15) */
            .deviceId = 0,                    /* JESD204B Configuration Device ID - link identification number. (Valid 0..255) */
            .lane0Id = 0,                    /* JESD204B Configuration starting Lane ID.  If more than one lane used, each lane will increment from the Lane0 ID. (Valid 0..31) */
            .M = 4,                            /* number of ADCs (0, 2, or 4) - 2 ADCs per receive chain */
            .K = 32,                        /* number of frames in a multiframe (default=32), F*K must be a multiple of 4. (F=2*M/numberOfLanes) */
            .F = 4,                            /* F (number of bytes per frame) */
            .Np = 16,                            /* Np (converter sample resolution) */
            .scramble = 1,                    /* scrambling off if framerScramble= 0, if framerScramble>0 scramble is enabled. */
            .externalSysref = 1,            /* 0=use internal SYSREF, 1= use external SYSREF */
            .serializerLanesEnabled = 0x03,    /* serializerLanesEnabled - bit per lane, [0] = Lane0 enabled, [1] = Lane1 enabled */
            .serializerLaneCrossbar = 0xE4,    /* serializerLaneCrossbar */
            .lmfcOffset = 31,                /* lmfcOffset - LMFC offset value for deterministic latency setting */
            .newSysrefOnRelink = 0,            /* newSysrefOnRelink */
            .syncbInSelect = 0,                /* syncbInSelect; */
            .overSample = 0,                    /* 1=overSample, 0=bitRepeat */
            .syncbInLvdsMode = 1,
            .syncbInLvdsPnInvert = 0,
            .enableManualLaneXbar = 0 /* 0=auto, 1=manual */
        },
        /* Framer B settings */
        .framerB = 
        {
            .bankId = 0,                    /* JESD204B Configuration Bank ID -extension to Device ID (Valid 0..15) */
            .deviceId = 0,                    /* JESD204B Configuration Device ID - link identification number. (Valid 0..255) */
            .lane0Id = 0,                    /* JESD204B Configuration starting Lane ID.  If more than one lane used, each lane will increment from the Lane0 ID. (Valid 0..31) */
            .M = 2,                            /* number of ADCs (0, 2, or 4) - 2 ADCs per receive chain */
            .K = 32,                        /* number of frames in a multiframe (default=32), F*K must be a multiple of 4. (F=2*M/numberOfLanes) */
            .F = 2,                            /* F (number of bytes per frame) */
            .Np = 16,                            /* Np (converter sample resolution) */
            .scramble = 1,                    /* scrambling off if framerScramble= 0, if framerScramble>0 scramble is enabled. */
            .externalSysref = 1,            /* 0=use internal SYSREF, 1= use external SYSREF */
            .serializerLanesEnabled = 0x0C,    /* serializerLanesEnabled - bit per lane, [0] = Lane0 enabled, [1] = Lane1 enabled */
            .serializerLaneCrossbar = 0xE4,    /* serializerLaneCrossbar */
            .lmfcOffset = 31,                /* lmfcOffset - LMFC offset value for deterministic latency setting */
            .newSysrefOnRelink = 0,            /* newSysrefOnRelink */
            .syncbInSelect = 1,                /* syncbInSelect; */
            .overSample = 0,                    /* 1=overSample, 0=bitRepeat */
            .syncbInLvdsMode = 1,
            .syncbInLvdsPnInvert = 0,
            .enableManualLaneXbar = 0 /* 0=auto, 1=manual */
        },
        /* Deframer A settings */
        .deframerA = 
        {
            .bankId = 0,                    /* bankId extension to Device ID (Valid 0..15) */
            .deviceId = 0,                    /* deviceId  link identification number. (Valid 0..255) */
            .lane0Id = 0,                    /* lane0Id Lane0 ID. (Valid 0..31) */
            .M = 4,                            /* M  number of DACss (0, 2, or 4) - 2 DACs per transmit chain */
            .K = 32,                        /* K  #frames in a multiframe (default=32), F*K=multiple of 4. (F=2*M/numberOfLanes) */
            .scramble = 1,                    /* scramble  scrambling off if scramble= 0 */
            .externalSysref = 1,            /* externalSysref  0= use internal SYSREF, 1= external SYSREF */
            .deserializerLanesEnabled = 0x0F,    /* deserializerLanesEnabled  bit per lane, [0] = Lane0 enabled */
            .deserializerLaneCrossbar = 0xE4,    /* deserializerLaneCrossbar */
            .lmfcOffset = 17,                /* lmfcOffset	 LMFC offset value to adjust deterministic latency */
            .newSysrefOnRelink = 0,            /* newSysrefOnRelink */
            .syncbOutSelect = 0,                /* SYNCBOUT0/1 select */
            .Np = 16,                /* Np (converter sample resolution) */
            .syncbOutLvdsMode = 1,
            .syncbOutLvdsPnInvert = 0,
            .syncbOutCmosSlewRate = 0,
            .syncbOutCmosDriveLevel = 0,
            .enableManualLaneXbar = 0 /* 0=auto, 1=manual */
        },
        /* Deframer B settings */
        .deframerB = 
        {
            .bankId = 0,                    /* bankId extension to Device ID (Valid 0..15) */
            .deviceId = 0,                    /* deviceId  link identification number. (Valid 0..255) */
            .lane0Id = 0,                    /* lane0Id Lane0 ID. (Valid 0..31) */
            .M = 0,                            /* M  number of DACss (0, 2, or 4) - 2 DACs per transmit chain */
            .K = 32,                        /* K  #frames in a multiframe (default=32), F*K=multiple of 4. (F=2*M/numberOfLanes) */
            .scramble = 1,                    /* scramble  scrambling off if scramble= 0 */
            .externalSysref = 1,            /* externalSysref  0= use internal SYSREF, 1= external SYSREF */
            .deserializerLanesEnabled = 0x00,    /* deserializerLanesEnabled  bit per lane, [0] = Lane0 enabled */
            .deserializerLaneCrossbar = 0xE4,    /* deserializerLaneCrossbar */
            .lmfcOffset = 0,                /* lmfcOffset	 LMFC offset value to adjust deterministic latency */
            .newSysrefOnRelink = 0,            /* newSysrefOnRelink */
            .syncbOutSelect = 1,                /* SYNCBOUT0/1 select */
            .Np = 16,                /* Np (converter sample resolution) */
            .syncbOutLvdsMode = 1,
            .syncbOutLvdsPnInvert = 0,
            .syncbOutCmosSlewRate = 0,
            .syncbOutCmosDriveLevel = 0,
            .enableManualLaneXbar = 0 /* 0=auto, 1=manual */
        },
        .serAmplitude = 15,                    /* Serializer amplitude setting. Default = 15. Range is 0..15 */
        .serPreEmphasis = 1,                /* Serializer pre-emphasis setting. Default = 1 Range is 0..4 */
        .serInvertLanePolarity = 0,            /* Serializer Lane PN inversion select. Default = 0. Where, bit[0] = 1 will invert lane [0], bit[1] = 1 will invert lane 1, etc. */
        .desInvertLanePolarity = 0,            /* Deserializer Lane PN inversion select.  bit[0] = 1 Invert PN of Lane 0, bit[1] = Invert PN of Lane 1, etc */
        .desEqSetting = 1,                    /* Deserializer Equalizer setting. Applied to all deserializer lanes. Range is 0..4 */
        .sysrefLvdsMode = 1,                /* Use LVDS inputs on Talise for SYSREF */
        .sysrefLvdsPnInvert = 0              /*0= Do not PN invert SYSREF */
    }
};

//Only needs to be called if user wants to setup AGC parameters
static taliseAgcCfg_t rxAgcCtrl =
{
    4,
    255,
    195,
    255,
    195,
    30720,  /* AGC gain update time in us (125us-250us - based on IQ data rate - set for 125us @ 245.76 Mhz) */
    10,
    10,
    16,
    0,
    1,
    0,
    0,
    0,
    1,
    31,
    246,
    4,
    1,          /*!<1- bit field to enable the multiple time constants in AGC loop for fast attack and fast recovery to max gain. */
    /* agcPower */
    {
        1,      /*!<1-bit field, enables the Rx power measurement block. */
        1,      /*!<1-bit field, allows using Rx PFIR for power measurement. */
        0,      /*!<1-bit field, allows to use the output of the second digital offset block in the Rx datapath for power measurement. */
        9,      /*!<AGC power measurement detect lower 0 threshold. Default = -12dBFS == 5, 7-bit register value where max = 0x7F, min = 0x00 */
        2,      /*!<AGC power measurement detect lower 1 threshold. Default = (offset) 4dB == 0, 4-bit register value where  max = 0xF, min = 0x00 */
        4,      /*!<AGC power measurement detect lower 0 recovery gain step. Default = 2dB - based on gain table step  size, 5-bit register value where max = 0x1F, min = 0x00 */
        4,      /*!<AGC power measurement detect lower 1 recovery gain step. Default = 4dB - based on gain table step size, 5-bit register value where max = 0x1F, min = 0x00 */
        5,      /*!< power measurement duration used by the decimated power block. Default = 0x05, 5-bit register value where max = 0x1F, min = 0x00 */
        5,      /*!<Allows power detection of data for a specific slice of the gain update counter. 16-bit register value (currently not used) */
        1,      /*!<Allows power detection of data for a specific slice of the gain update counter. 16-bit register value (currently not used) */
        5,      /*!<Allows power detection of data for a specific slice of the gain update counter. 16-bit register value (currently not used) */
        1,      /*!<Allows power detection of data for a specific slice of the gain update counter. 16-bit register value (currently not used) */
        2,      /*!<Default value should be 2*/
        0,
        0
    },
    /* agcPeak */
    {
        205,        /*!<1st update interval for the multiple time constant in AGC loop mode, Default:205. */
        2,          /*!<sets the 2nd update interval for the multiple time constant in AGC loop mode. Calculated as a multiple of  agcUnderRangeLowInterval  , Default: 4 */
        4,          /*!<sets the 3rd update interval for the multiple time constant in AGC loop mode. Calculated as a multiple of agcUnderRangeMidInterval and agcUnderRangeLowInterval, Default: 4 */
        39,         /*!<AGC APD high threshold. Default=0x1F, 6-bit register value where max=0x3F, min =0x00 */
        49,         /*!<AGC APD peak detect high threshold. default = 0x1F, 6-bit register value where max = 0x3F, min = 0x00.  Set to 3dB below apdHighThresh */
        23,         /*!<AGC APD peak detect low threshold. default = 3dB below high threshold, 6-bit register value where max =0x3F, min = 0x00 */
        19,         /*!<AGC APD peak detect low threshold. default = 3dB below high threshold, 6-bit register value where max = 0x3F, min = 0x00 . Set to 3dB below apdLowThresh  */
        6,          /*!<AGC APD peak detect upper threshold count. Default = 0x06 8-bit register value where max = 0xFF, min = 0x20  */
        3,          /*!<AGC APD peak detect lower threshold count. Default = 0x03, 8-bit register value where max = 0xFF, min = 0x00  */
        4,          /*!<AGC APD peak detect attack gain step. Default = 2dB step - based on gain table step size, 5-bit register  value, where max = 0x1F, min = 0x00  */
        2,          /*!<AGC APD gain index step size. Recommended to be same as hb2GainStepRecovery. Default = 0x00, 5-bit register value where max = 0x1F, min = 0x00  */
        1,          /*!<1-bit field, enables or disables the HB2 overload detector.  */
        1,          /*!<3-bit field. Sets the window of clock cycles (at the HB2 output rate) to meet the overload count. */
        1,          /*!<4-bit field. Sets the number of actual overloads required to trigger the overload signal.  */
        181,        /*!<AGC decimator output high threshold. Default = 0xB5, 8-bit register value where max = 0xFF, min = 0x00 */
        45,         /*!<AGC decimator output low threshold. Default = 0x80, 8-bit register value where max = 0xFF, min = 0x00 */
        90,         /*!<AGC decimator output low threshold. Default = 0x80, 8-bit register value where max = 0xFF, min = 0x00 */
        128,        /*!<AGC decimator output low threshold. Default = 0x80, 8-bit register value where max = 0xFF, min = 0x00 */
        6,          /*!<AGC HB2 output upper threshold count. Default = 0x06, 8-bit register value where max = 0xFF, min =  0x20 */
        3,          /*!<AGC HB2 output lower threshold count. Default = 0x03, 8-bit register value where max = 0xFF, min = 0x00 */
        2,          /*!<AGC decimator gain index step size. Default = 0x00, 5-bit register value where max = 0x1F, min = 0x00 */
        4,          /*!<AGC HB2 gain index step size, when the HB2 Low Overrange interval 0 triggers a programmable number  of times. Default = 0x08, 5-bit register value where max = 0x1F, min = 0x00 */
        8,          /*!<AGC HB2 gain index step size, when the HB2 Low Overrange interval 1 triggers a programmable number of times. Default = 0x04, 5-bit register value where max = 0x1F, min = 0x00 */
        4,          /*!<AGC decimator output attack gain step. Default = 2dB step - based on gain table step size, 5-bit register value, where max = 0x1F, min = 0x00 */
        1,
        0,
        0
    }
};

#include <dt-bindings/iio/frequency/ad9528.h>
#include <dt-bindings/gpio/gpio.h>
#include <dt-bindings/interrupt-controller/irq.h>

/ {
	clocks {
		adrv9009_clkin: clock@0 {
			#clock-cells = <0>;
			compatible = "fixed-clock";
			clock-frequency = <15360000>;
			clock-output-names = "adrv9009_ext_refclk";
		};
	};
};

&hpc1_spi {

	clk1_ad9528: ad9528-1@0 {
		#address-cells = <1>;
		#size-cells = <0>;
		#clock-cells = <1>;
		compatible = "ad9528";

		spi-max-frequency = <10000000>;
		//adi,spi-3wire-enable;
		reg = <0>;

		clock-output-names = "ad9528-1_out0", "ad9528-1_out1", "ad9528-1_out2",
			"ad9528-1_out3", "ad9528-1_out4", "ad9528-1_out5", "ad9528-1_out6",
			"ad9528-1_out7", "ad9528-1_out8", "ad9528-1_out9", "ad9528-1_out10",
			"ad9528-1_out11", "ad9528-1_out12", "ad9528-1_out13";

		adi,vcxo-freq = <122880000>;

		adi,refa-enable;
		adi,refa-diff-rcv-enable;
		adi,refa-r-div = <1>;
		adi,osc-in-cmos-neg-inp-enable;

		/* PLL1 config */
		adi,pll1-feedback-div = <4>;
		adi,pll1-charge-pump-current-nA = <5000>;

		/* PLL2 config */
		adi,pll2-vco-div-m1 = <3>; /* use 5 for 184320000 output device clock */
		adi,pll2-n2-div = <10>; /* N / M1 */
		adi,pll2-r1-div = <1>;
		adi,pll2-charge-pump-current-nA = <805000>;

		/* SYSREF config */
		adi,sysref-src = <SYSREF_SRC_INTERNAL>;
		adi,sysref-pattern-mode = <SYSREF_PATTERN_CONTINUOUS>;
		adi,sysref-k-div = <512>;
		adi,sysref-request-enable;
		adi,sysref-nshot-mode = <SYSREF_NSHOT_4_PULSES>;
		adi,sysref-request-trigger-mode = <SYSREF_LEVEL_HIGH>;

		adi,rpole2 = <RPOLE2_900_OHM>;
		adi,rzero = <RZERO_1850_OHM>;
		adi,cpole1 = <CPOLE1_16_PF>;

		adi,status-mon-pin0-function-select = <1>; /* PLL1 & PLL2 Locked */
		adi,status-mon-pin1-function-select = <7>; /* REFA Correct */

		ad9528_1_c13: channel@13 {
			reg = <13>;
			adi,extended-name = "DEV_CLK";
			adi,driver-mode = <DRIVER_MODE_LVDS>;
			adi,divider-phase = <0>;
			adi,channel-divider = <8>;
			adi,signal-source = <SOURCE_VCO>;
		};

		ad9528_1_c1: channel@1 {
			reg = <1>;
			adi,extended-name = "FMC_CLK";
			adi,driver-mode = <DRIVER_MODE_LVDS>;
			adi,divider-phase = <0>;
			adi,channel-divider = <8>;
			adi,signal-source = <SOURCE_VCO>;
		};

		ad9528_1_c12: channel@12 {
			reg = <12>;
			adi,extended-name = "DEV_SYSREF";
			adi,driver-mode = <DRIVER_MODE_LVDS>;
			adi,divider-phase = <0>;
			adi,channel-divider = <8>;
			adi,signal-source = <SOURCE_SYSREF_VCO>;
		};

		ad9528_1_c3: channel@3 {
			reg = <3>;
			adi,extended-name = "FMC_SYSREF";
			adi,driver-mode = <DRIVER_MODE_LVDS>;
			adi,divider-phase = <0>;
			adi,channel-divider = <8>;
			adi,signal-source = <SOURCE_SYSREF_VCO>;
		};
	};

	trx1_adrv9009: adrv9009-phy-1@1 {
		#address-cells = <1>;
		#size-cells = <0>;
		#clock-cells = <1>;
		compatible = "adrv9009";

		/* SPI Setup */
		reg = <1>;
		spi-max-frequency = <25000000>;

		interrupt-parent = <&gpio>;
		interrupts = <120 IRQ_TYPE_EDGE_RISING>;

		/* Clocks */
		clocks = <&axi_adrv9009_rx_jesd_1>, <&axi_adrv9009_tx_jesd_1>,
			<&axi_adrv9009_rx_os_jesd_1>, <&clk1_ad9528 13>, <&clk1_ad9528 1>;
		clock-names = "jesd_rx_clk", "jesd_tx_clk", "jesd_rx_os_clk", "dev_clk", "fmc_clk";
		clock-output-names = "rx_sampl_clk_1", "rx_os_sampl_clk_1", "tx_sampl_clk_1";

		/* JESD204 */

		/* JESD204 RX */
		adi,jesd204-framer-a-bank-id = <1>;
		adi,jesd204-framer-a-device-id = <0>;
		adi,jesd204-framer-a-lane0-id = <0>;
		adi,jesd204-framer-a-m = <4>;
		adi,jesd204-framer-a-k = <32>;
		adi,jesd204-framer-a-f = <4>;
		adi,jesd204-framer-a-np = <16>;
		adi,jesd204-framer-a-scramble = <1>;
		adi,jesd204-framer-a-external-sysref = <1>;
		adi,jesd204-framer-a-serializer-lanes-enabled = <0x03>;
		adi,jesd204-framer-a-serializer-lane-crossbar = <0xE4>;
		adi,jesd204-framer-a-lmfc-offset = <31>;
		adi,jesd204-framer-a-new-sysref-on-relink = <0>;
		adi,jesd204-framer-a-syncb-in-select = <0>;
		adi,jesd204-framer-a-over-sample = <0>;
		adi,jesd204-framer-a-syncb-in-lvds-mode = <1>;
		adi,jesd204-framer-a-syncb-in-lvds-pn-invert = <0>;
		adi,jesd204-framer-a-enable-manual-lane-xbar = <0>;

		/* JESD204 OBS */
		adi,jesd204-framer-b-bank-id = <0>;
		adi,jesd204-framer-b-device-id = <0>;
		adi,jesd204-framer-b-lane0-id = <0>;
		adi,jesd204-framer-b-m = <2>;
		adi,jesd204-framer-b-k = <32>;
		adi,jesd204-framer-b-f = <2>;
		adi,jesd204-framer-b-np = <16>;
		adi,jesd204-framer-b-scramble = <1>;
		adi,jesd204-framer-b-external-sysref = <1>;
		adi,jesd204-framer-b-serializer-lanes-enabled = <0x0C>;
		adi,jesd204-framer-b-serializer-lane-crossbar = <0xE4>;
		adi,jesd204-framer-b-lmfc-offset = <31>;
		adi,jesd204-framer-b-new-sysref-on-relink = <0>;
		adi,jesd204-framer-b-syncb-in-select = <1>;
		adi,jesd204-framer-b-over-sample = <0>;
		adi,jesd204-framer-b-syncb-in-lvds-mode = <1>;
		adi,jesd204-framer-b-syncb-in-lvds-pn-invert = <0>;
		adi,jesd204-framer-b-enable-manual-lane-xbar = <0>;

		/* JESD204 TX */
		adi,jesd204-deframer-a-bank-id = <0>;
		adi,jesd204-deframer-a-device-id = <0>;
		adi,jesd204-deframer-a-lane0-id = <0>;
		adi,jesd204-deframer-a-m = <4>;
		adi,jesd204-deframer-a-k = <32>;
		adi,jesd204-deframer-a-scramble = <1>;
		adi,jesd204-deframer-a-external-sysref = <1>;
		adi,jesd204-deframer-a-deserializer-lanes-enabled = <0x0F>;
		adi,jesd204-deframer-a-deserializer-lane-crossbar = <0xE4>;
		adi,jesd204-deframer-a-lmfc-offset = <17>;
		adi,jesd204-deframer-a-new-sysref-on-relink = <0>;
		adi,jesd204-deframer-a-syncb-out-select = <0>;
		adi,jesd204-deframer-a-np = <16>;
		adi,jesd204-deframer-a-syncb-out-lvds-mode = <1>;
		adi,jesd204-deframer-a-syncb-out-lvds-pn-invert = <0>;
		adi,jesd204-deframer-a-syncb-out-cmos-slew-rate = <0>;
		adi,jesd204-deframer-a-syncb-out-cmos-drive-level = <0>;
		adi,jesd204-deframer-a-enable-manual-lane-xbar = <0>;

		adi,jesd204-ser-amplitude = <15>;
		adi,jesd204-ser-pre-emphasis = <1>;
		adi,jesd204-ser-invert-lane-polarity = <0>;
		adi,jesd204-des-invert-lane-polarity = <0>;
		adi,jesd204-des-eq-setting = <1>;
		adi,jesd204-sysref-lvds-mode = <1>;
		adi,jesd204-sysref-lvds-pn-invert = <0>;

		/* RX */

		adi,rx-profile-rx-fir-gain_db = <(-6)>;
		adi,rx-profile-rx-fir-num-fir-coefs = <48>;
		adi,rx-profile-rx-fir-coefs = /bits/ 16 <(-1) (0) (4) (1) (-16) (-6) (49) (23) (-124) (-67) (274) (168) (-542) (-378) (985) (784) (-1689) (-1553) (2805) (3067) (-4859) (-7088) (9643) (31289) (31289) (9643) (-7088) (-4859) (3067) (2805) (-1553) (-1689) (784) (985) (-378) (-542) (168) (274) (-67) (-124) (23) (49) (-6) (-16) (1) (4) (0) (-1)>;

		adi,rx-profile-rx-fir-decimation = <2>;
		adi,rx-profile-rx-dec5-decimation = <4>;
		adi,rx-profile-rhb1-decimation = <1>;
		adi,rx-profile-rx-output-rate_khz = <153600>;
		adi,rx-profile-rf-bandwidth_hz = <100000000>;
		adi,rx-profile-rx-bbf3d-bcorner_khz = <100000>;
		adi,rx-profile-rx-adc-profile = /bits/ 16 <341 221 181 90 1280 699 1282 58 863 21 568 27 48 31 22 201 0 0 0 0 50 0 6 4 43 0 6 4 43 0 25 3 0 0 25 3 0 0 165 44 31 905>;
		adi,rx-profile-rx-ddc-mode = <0>;

		adi,rx-nco-shifter-band-a-input-band-width_khz = <0>;
		adi,rx-nco-shifter-band-a-input-center-freq_khz = <0>;
		adi,rx-nco-shifter-band-a-nco1-freq_khz = <0>;
		adi,rx-nco-shifter-band-a-nco2-freq_khz = <0>;
		adi,rx-nco-shifter-band-binput-band-width_khz = <0>;
		adi,rx-nco-shifter-band-binput-center-freq_khz = <0>;
		adi,rx-nco-shifter-band-bnco1-freq_khz = <0>;
		adi,rx-nco-shifter-band-bnco2-freq_khz = <0>;

		adi,rx-gain-control-gain-mode = <0>;
		adi,rx-gain-control-rx1-gain-index = <255>;
		adi,rx-gain-control-rx2-gain-index = <255>;
		adi,rx-gain-control-rx1-max-gain-index = <255>;
		adi,rx-gain-control-rx1-min-gain-index = <195>;
		adi,rx-gain-control-rx2-max-gain-index = <255>;
		adi,rx-gain-control-rx2-min-gain-index = <195>;

		adi,rx-settings-framer-sel = <0>;
		adi,rx-settings-rx-channels = <3>;

		/* ORX */

		adi,orx-profile-rx-fir-gain_db = <6>;
		adi,orx-profile-rx-fir-num-fir-coefs = <24>;
		adi,orx-profile-rx-fir-coefs = /bits/ 16  <(32) (-15) (19) (-22) (20) (-17) (-21) (59) (-163) (435) (-1731) (19255) (-1731) (435) (-163) (59) (-21) (-17) (20) (-22) (19) (-15) (32) (0)>;
		adi,orx-profile-rx-fir-decimation = <1>;
		adi,orx-profile-rx-dec5-decimation = <4>;
		adi,orx-profile-rhb1-decimation = <1>;
		adi,orx-profile-orx-output-rate_khz = <307200>;
		adi,orx-profile-rf-bandwidth_hz = <277000000>;
		adi,orx-profile-rx-bbf3d-bcorner_khz = <138500>;
		adi,orx-profile-orx-low-pass-adc-profile = /bits/ 16  <259 249 181 90 1280 1180 1517 306 891 81 610 10 48 30 23 215 0 0 0 0 54 0 7 5 26 0 7 5 26 0 25 3 0 0 25 3 0 0 165 44 15 905>;
		adi,orx-profile-orx-band-pass-adc-profile = /bits/ 16  <210 131 181 90 1280 2828 1423 0 694 535 610 111 1 11 18 186 0 0 0 0 47 0 7 5 26 0 7 5 26 0 25 3 0 0 25 3 0 0 165 44 15 905>;
		adi,orx-profile-orx-ddc-mode = <0>;
		adi,orx-profile-orx-merge-filter = /bits/ 16  <(42) (326) (-447) (-124) (933) (-774) (-806) (2267) (-1039) (-3716) (9469) (20704)>;

		adi,orx-gain-control-gain-mode = <0>;
		adi,orx-gain-control-orx1-gain-index = <255>;
		adi,orx-gain-control-orx2-gain-index = <255>;
		adi,orx-gain-control-orx1-max-gain-index = <255>;
		adi,orx-gain-control-orx1-min-gain-index = <195>;
		adi,orx-gain-control-orx2-max-gain-index = <255>;
		adi,orx-gain-control-orx2-min-gain-index = <195>;

		adi,obs-settings-framer-sel = <1>;
		adi,obs-settings-obs-rx-channels-enable = <3>;
		adi,obs-settings-obs-rx-lo-source = <0>;

		/* TX */

		adi,tx-profile-tx-fir-gain_db = <6>;
		adi,tx-profile-tx-fir-num-fir-coefs = <20>;
		adi,tx-profile-tx-fir-coefs = /bits/ 16  <(-15) (22) (-41) (83) (-145) (259) (-518) (1199) (-2619) (19936) (-2619) (1199) (-518) (259) (-145) (83) (-41) (22) (-15) (0)>;

		adi,tx-profile-dac-div = <1>;

		adi,tx-profile-tx-fir-interpolation = <1>;
		adi,tx-profile-thb1-interpolation = <2>;
		adi,tx-profile-thb2-interpolation = <2>;
		adi,tx-profile-thb3-interpolation = <1>;
		adi,tx-profile-tx-int5-interpolation = <1>;
		adi,tx-profile-tx-input-rate_khz = <307200>;
		adi,tx-profile-primary-sig-bandwidth_hz = <100000000>;
		adi,tx-profile-rf-bandwidth_hz = <277000000>;
		adi,tx-profile-tx-dac3d-bcorner_khz = <277000>;
		adi,tx-profile-tx-bbf3d-bcorner_khz = <138500>;
		adi,tx-profile-loop-back-adc-profile = /bits/ 16 <283 243 181 90 1280 1027 1491 276 885 66 609 15 48 30 23 214 0 0 0 0 54 0 7 5 26 0 7 5 26 0 25 3 0 0 25 3 0 0 165 44 15 905>;

		adi,tx-settings-deframer-sel = <0>;
		adi,tx-settings-tx-channels = <3>;
		adi,tx-settings-tx-atten-step-size = <0>;
		adi,tx-settings-tx1-atten_md-b = <10000>;
		adi,tx-settings-tx2-atten_md-b = <10000>;
		adi,tx-settings-dis-tx-data-if-pll-unlock = <0>;

		/* Clocks */

		adi,dig-clocks-device-clock_khz = <153600>;
		adi,dig-clocks-clk-pll-vco-freq_khz = <12288000>;
		adi,dig-clocks-clk-pll-hs-div = <4>;
		adi,dig-clocks-rf-pll-use-external-lo = <0>;
		adi,dig-clocks-rf-pll-phase-sync-mode = <3>;

		/* AGC */

		adi,rxagc-peak-agc-under-range-low-interval_ns = <205>;
		adi,rxagc-peak-agc-under-range-mid-interval = <2>;
		adi,rxagc-peak-agc-under-range-high-interval = <4>;
		adi,rxagc-peak-apd-high-thresh = <39>;
		adi,rxagc-peak-apd-low-gain-mode-high-thresh = <49>;
		adi,rxagc-peak-apd-low-thresh = <23>;
		adi,rxagc-peak-apd-low-gain-mode-low-thresh = <19>;
		adi,rxagc-peak-apd-upper-thresh-peak-exceeded-cnt = <6>;
		adi,rxagc-peak-apd-lower-thresh-peak-exceeded-cnt = <3>;
		adi,rxagc-peak-apd-gain-step-attack = <4>;
		adi,rxagc-peak-apd-gain-step-recovery = <2>;
		adi,rxagc-peak-enable-hb2-overload = <1>;
		adi,rxagc-peak-hb2-overload-duration-cnt = <1>;
		adi,rxagc-peak-hb2-overload-thresh-cnt = <1>;
		adi,rxagc-peak-hb2-high-thresh = <181>;
		adi,rxagc-peak-hb2-under-range-low-thresh = <45>;
		adi,rxagc-peak-hb2-under-range-mid-thresh = <90>;
		adi,rxagc-peak-hb2-under-range-high-thresh = <128>;
		adi,rxagc-peak-hb2-upper-thresh-peak-exceeded-cnt = <6>;
		adi,rxagc-peak-hb2-lower-thresh-peak-exceeded-cnt = <3>;
		adi,rxagc-peak-hb2-gain-step-high-recovery = <2>;
		adi,rxagc-peak-hb2-gain-step-low-recovery = <4>;
		adi,rxagc-peak-hb2-gain-step-mid-recovery = <8>;
		adi,rxagc-peak-hb2-gain-step-attack = <4>;
		adi,rxagc-peak-hb2-overload-power-mode = <1>;
		adi,rxagc-peak-hb2-ovrg-sel = <0>;
		adi,rxagc-peak-hb2-thresh-config = <0>;

		adi,rxagc-power-power-enable-measurement = <1>;
		adi,rxagc-power-power-use-rfir-out = <1>;
		adi,rxagc-power-power-use-bbdc2 = <0>;
		adi,rxagc-power-under-range-high-power-thresh = <9>;
		adi,rxagc-power-under-range-low-power-thresh = <2>;
		adi,rxagc-power-under-range-high-power-gain-step-recovery = <4>;
		adi,rxagc-power-under-range-low-power-gain-step-recovery = <4>;
		adi,rxagc-power-power-measurement-duration = <5>;
		adi,rxagc-power-rx1-tdd-power-meas-duration = <5>;
		adi,rxagc-power-rx1-tdd-power-meas-delay = <1>;
		adi,rxagc-power-rx2-tdd-power-meas-duration = <5>;
		adi,rxagc-power-rx2-tdd-power-meas-delay = <1>;
		adi,rxagc-power-upper0-power-thresh = <2>;
		adi,rxagc-power-upper1-power-thresh = <0>;
		adi,rxagc-power-power-log-shift = <0>;

		adi,rxagc-agc-peak-wait-time = <4>;
		adi,rxagc-agc-rx1-max-gain-index = <255>;
		adi,rxagc-agc-rx1-min-gain-index = <195>;
		adi,rxagc-agc-rx2-max-gain-index = <255>;
		adi,rxagc-agc-rx2-min-gain-index = <195>;
		adi,rxagc-agc-gain-update-counter_us = <30720>;
		adi,rxagc-agc-rx1-attack-delay = <10>;
		adi,rxagc-agc-rx2-attack-delay = <10>;
		adi,rxagc-agc-slow-loop-settling-delay = <16>;
		adi,rxagc-agc-low-thresh-prevent-gain = <0>;
		adi,rxagc-agc-change-gain-if-thresh-high = <1>;
		adi,rxagc-agc-peak-thresh-gain-control-mode = <0>;
		adi,rxagc-agc-reset-on-rxon = <0>;
		adi,rxagc-agc-enable-sync-pulse-for-gain-counter = <0>;
		adi,rxagc-agc-enable-ip3-optimization-thresh = <1>;
		adi,rxagc-ip3-over-range-thresh = <31>;
		adi,rxagc-ip3-over-range-thresh-index = <246>;
		adi,rxagc-ip3-peak-exceeded-cnt = <4>;
		adi,rxagc-agc-enable-fast-recovery-loop = <1>;


		/* Misc */

		adi,aux-dac-enables = <0x00>; /* Mask */

		adi,aux-dac-vref0 = <3>;
		adi,aux-dac-resolution0 = <0>;
		adi,aux-dac-values0 = <0>;
		adi,aux-dac-vref1 = <3>;
		adi,aux-dac-resolution1 = <0>;
		adi,aux-dac-values1 = <0>;
		adi,aux-dac-vref2 = <3>;
		adi,aux-dac-resolution2 = <0>;
		adi,aux-dac-values2 = <0>;
		adi,aux-dac-vref3 = <3>;
		adi,aux-dac-resolution3 = <0>;
		adi,aux-dac-values3 = <0>;
		adi,aux-dac-vref4 = <3>;
		adi,aux-dac-resolution4 = <0>;
		adi,aux-dac-values4 = <0>;
		adi,aux-dac-vref5 = <3>;
		adi,aux-dac-resolution5 = <0>;
		adi,aux-dac-values5 = <0>;
		adi,aux-dac-vref6 = <3>;
		adi,aux-dac-resolution6 = <0>;
		adi,aux-dac-values6 = <0>;
		adi,aux-dac-vref7 = <3>;
		adi,aux-dac-resolution7 = <0>;
		adi,aux-dac-values7 = <0>;
		adi,aux-dac-vref8 = <3>;
		adi,aux-dac-resolution8 = <0>;
		adi,aux-dac-values8 = <0>;
		adi,aux-dac-vref9 = <3>;
		adi,aux-dac-resolution9 = <0>;
		adi,aux-dac-values9 = <0>;
		adi,aux-dac-vref10 = <3>;
		adi,aux-dac-resolution10 = <0>;
		adi,aux-dac-values10 = <0>;
		adi,aux-dac-vref11 = <3>;
		adi,aux-dac-resolution11 = <0>;
		adi,aux-dac-values11 = <0>;

		adi,arm-gpio-config-orx1-tx-sel0-pin-gpio-pin-sel = <0>;
		adi,arm-gpio-config-orx1-tx-sel0-pin-polarity = <0>;
		adi,arm-gpio-config-orx1-tx-sel0-pin-enable = <0>;

		adi,arm-gpio-config-orx1-tx-sel1-pin-gpio-pin-sel = <0>;
		adi,arm-gpio-config-orx1-tx-sel1-pin-polarity = <0>;
		adi,arm-gpio-config-orx1-tx-sel1-pin-enable = <0>;
		adi,arm-gpio-config-orx2-tx-sel0-pin-gpio-pin-sel = <0>;
		adi,arm-gpio-config-orx2-tx-sel0-pin-polarity = <0>;
		adi,arm-gpio-config-orx2-tx-sel0-pin-enable = <0>;

		adi,arm-gpio-config-orx2-tx-sel1-pin-gpio-pin-sel = <0>;
		adi,arm-gpio-config-orx2-tx-sel1-pin-polarity = <0>;
		adi,arm-gpio-config-orx2-tx-sel1-pin-enable = <0>;
		adi,arm-gpio-config-en-tx-tracking-cals-gpio-pin-sel = <0>;
		adi,arm-gpio-config-en-tx-tracking-cals-polarity = <0>;
		adi,arm-gpio-config-en-tx-tracking-cals-enable = <0>;

		adi,orx-lo-cfg-disable-aux-pll-relocking = <0>;
		adi,orx-lo-cfg-gpio-select = <19>;

		adi,fhm-config-fhm-gpio-pin = <0>;
		adi,fhm-config-fhm-min-freq_mhz = <100>;
		adi,fhm-config-fhm-max-freq_mhz = <100>;

		adi,fhm-mode-fhm-enable = <0>;
		adi,fhm-mode-enable-mcs-sync = <0>;
		adi,fhm-mode-fhm-trigger-mode = <0>;
		adi,fhm-mode-fhm-exit-mode = <0>;
		adi,fhm-mode-fhm-init-frequency_hz = <2300000000>;

		adi,rx1-gain-ctrl-pin-inc-step = <1>;
		adi,rx1-gain-ctrl-pin-dec-step = <1>;
		adi,rx1-gain-ctrl-pin-rx-gain-inc-pin = <0>;
		adi,rx1-gain-ctrl-pin-rx-gain-dec-pin = <1>;
		adi,rx1-gain-ctrl-pin-enable = <0>;

		adi,rx2-gain-ctrl-pin-inc-step = <1>;
		adi,rx2-gain-ctrl-pin-dec-step = <1>;
		adi,rx2-gain-ctrl-pin-rx-gain-inc-pin = <3>;
		adi,rx2-gain-ctrl-pin-rx-gain-dec-pin = <4>;
		adi,rx2-gain-ctrl-pin-enable = <0>;

		adi,tx1-atten-ctrl-pin-step-size = <0>;
		adi,tx1-atten-ctrl-pin-tx-atten-inc-pin = <4>;
		adi,tx1-atten-ctrl-pin-tx-atten-dec-pin = <5>;
		adi,tx1-atten-ctrl-pin-enable = <0>;

		adi,tx2-atten-ctrl-pin-step-size = <0>;
		adi,tx2-atten-ctrl-pin-tx-atten-inc-pin = <6>;
		adi,tx2-atten-ctrl-pin-tx-atten-dec-pin = <7>;
		adi,tx2-atten-ctrl-pin-enable = <0>;

		adi,tx-pa-protection-avg-duration = <3>;
		adi,tx-pa-protection-tx-atten-step = <2>;
		adi,tx-pa-protection-tx1-power-threshold = <4096>;
		adi,tx-pa-protection-tx2-power-threshold = <4096>;
		adi,tx-pa-protection-peak-count = <4>;
		adi,tx-pa-protection-tx1-peak-threshold = <130>;
		adi,tx-pa-protection-tx2-peak-threshold = <130>;

		adi,trx-pll-lo-frequency_hz = <2300000000>;
		adi,aux-pll-lo-frequency_hz = <2300000000>;
	};
};

Thanks in advance,

Trung Nguyen