TES Connection Issues

For Full Recommended Setup Details

  • Read the User Guide provided at analog.com/ADRV9002
  • Under the ADRV9001 Evaluation Setup chapter we provide details on each element of the platform setup. Be certain that all elements of the setup (Host Computer, FPGA [ZC706 or ZCU102] and EVB) are configured exactly as specified in this document. If after confirming your setup is as detailed there, search through this document for the best match to your issue and attempt to run the debug steps we provide.

Connection Error

  • If the FPGA platform is connected through a router with DHCP enabled, the default IP address might need to be changed to the one assigned dynamically. This issue mostly affects the SW packages from v0.14 onwards and silicon revisions C0 and newer, Legacy SD card images (v0.12 and older) should not suffer from this issue as they did not support DHCP. The user will need to find the IP address assigned to the FPGA and use that in the TES Connection tab.
  • Not all versions of TES are compatible with every SD card image release or Device Driver release. Review the CHANGELOG.md and README.md files in the "ADRV9001 TES\" folder to determine which revisions of each package you should be using. A safe approach is to always use the latest release of TES (v0.15 and newer) with the latest SD card image and SW drivers. This works best on the latest silicon (C0 - released silicon) if you have access to that, however if you are using older silicon (B0 - pre-release silicon) you may need use the Legacy option in the SD card imaging tool provided here.
  • The ADRV9001 daughter card may be connected to the wrong FMC connector. Carefully review the User Guide to be certain you have the card on the correct connector as shown in Figure 1 or Figure 2. 


Figure 1. ZC706 FPGA with ADRV9002 Daughter Board


Figure 2, ZCU102 FPGA with ADRV9002 Daughter Board

  • There may be issues with the users Firewall blocking TES from communicating with the FPGA. Review the Firewall settings and make sure they are not blocking TES from connection. This is port 22 for the SSH connection to the FPGA and port 55557 for the TCP connection from the TES. 
  • Certain error messages can get “stuck” in TES log files. This can result in the TES flagging the same issue repeatedly even when there is nothing wrong. Completely uninstall ALL saved versions of TES and download all from scratch. Be sure to save any application critical edits made to the SDK or other files before deleting everything.
  • Our SW also expects that the ethernet address of the host computer is set to 192.168.1.2. Be certain that all elements of the setup (Computer, FPGA and Eval Board) are configured exactly as stated in the User Guide.

Server Failed to Start

  • Using PuTTY start a new SSH session with the following settings (if DHCP is not being used):

    • IP address: 192.168.1.10
    • Port: 22
    • Username: root
    • Password: analog

    Log into the FPGA and manually restart the ADRV9001 server at the following directory:

    • /home/analog/adrv9001_server/resources/Adi.Adrv9001.Server/
    • Execute command: ./Adrv9001Server_{Silicon Revision}_{Server Version}
    • The server may fail to start due to issues with the ADRV9001 daughter card. This is usually the fault of:
      • The daughter card is not getting a clk input. If the setup needs the onboard clk, ensure the clk switch at the top of the board is in the “Internal” position. Otherwise, keep the switch in the “External” position and double check your external clk supply. The “On Board TCXO Enabled” LED should indicate whether the onboard clk is successfully powered or not.
      • There may be some damage to the daughter card’s onboard power-management circuitry. The “Power Supply OK” LED is used to indicate whether the card’s power domains have been initialised successfully. If this LED is off there is likely an issue either with the ADP5056 chip used on the card, with one of the surrounding components or with the FPGA. Review our documentation regarding the daughter card’s power supply and power domains and attempt to debug the board and the FMC connector. It may be necessary to replace the ADP5056 if it is damaged.
    • The server may also fail to start in the event that the FPGA did not boot up correctly. Sometimes this can be a benign issue, simply power cycle the FPGA if either the LEDs next to the FPGA power switch or the System OK LED next to the Fan Header on the ADRV9001 daughter card are not behaving as specified in the User Guide.
    • If the SD Card image has been corrupted this may also prevent server launch. Check the “SD Card Image Corrupted” section of this document for more details.

SD Card Image Corrupted

  • We provide a guide on writing SD card images here: https://ez.analog.com/wide-band-rf-transceivers/tes-gui-software-support-adrv9001-adrv9007/w/documents/15476/sd-card-image We recommend you read this guide through and ensure that no step fails for you.
  • At minimum we recommend having a 16GB SDHC card, Spec Version 4. This should ensure you're not running into memory constraints on your platform.
  • Sometimes the SD Card image will be corrupted during file download in our SD card imaging tool. This problem will present itself as an error message during the Write to Device step of the SD Card imaging tool. An error message will be given similar to: “End of Central Reserve Cannot be Found” on Windows10 computers (different error messages have been seen on Windows7 machines, but we have little information on this behavior). If this error occurs, exit the imaging tool and delete the corrupted SD card image on your computer. Run the SD Card imaging tool again, being certain that you ran it both with elevated privileges and with a very stable internet connection.
  • Firewalls can prevent our tool from downloading the SD card image. Be sure that the firewall is not interfering with the SD card imaging tool.
  • Certain encryption software used by corporations to protect their data can encrypt data written to external devices such as SD cards. Be certain that either the encryption software is not interfering with the data transfer or that you have a workaround if you cannot disable the encryption software.
  • If the FPGA fails to boot repeatedly, it may be the case that the SD card has been corrupted due to an ill-timed platform shutdown. Reimage the SD card and try again.

Can't 'Ping' FPGA

  • Normally you should be able to get a ping response from the FPGA (192.168.1.10)
  • If you can't get a response from this address, first try to ensure that you can ping 192.168.1.2 (your PC). If you can't get a response from this address then ensure that your port is set up as described in the user guide
  • If you still can't get a response from 192.168.1.10, try ping "linaro-developer", the default FPGA hostname. You may receive a response from an IPv6 address. This is a known bug. To resolve this, log in to the FPGA with this IPv6 address and manually assign the FPGA address to 192.168.1.10.
  • One way to do this is as follows:
    • Log into FPGA with IPv6 address (or else use serial port)
    • Run $ ifconfig
    • We can see the „eth0“ interface but no IP Address assigned:
    • Navigate to network directory using $ cd../etc/network
    • Here we will want to make an edit to the interfaces file:
    • Using 'vim' or otherwise, make the following edits to the file:
      • Comment out the line 'iface eth0 inet dhcp' with a '#'
      • Add the following lines:
        • iface eth0 inet static
        • address 192.168.1.10
        • netmask 255.255.255.0
        • gateway 192.168.1.1
      • Save changes
    • Reboot platform and check that the correct IPv4 address has been assigned

General

  • The ADRV9001 daughter card requires an LVDS interface voltage of 1.8V. To achieve this, our SD card forces the ZC706 platform to operate outside of its normal operating parameters. If the SD card has not loaded properly, it is possible that the FPGA will provide a voltage to the interface that is sufficiently high enough to damage the daughter card. The System OK LED next to the Fan Header on the ADRV9001 daughter card will be RED if the interface voltage is too high. If you see this LED light up RED for a long duration, power down the FPGA and re-image the SD card. If this does not fix the issue, make certain that the FPGA is set up exactly as stated in the User Guide. Failing that, it is possible that either FPGA or the daughter card have some physical damage.
  • When the EVB and the FPGA are connected properly and the SD card is imaged correctly the LEDs will follow the following sequence after the FPGA is switched on:
    • On the FPGA the GPIO LEDs next to the switch will flash in sequence (one LED off at a time) 
    • on the EVB the overvoltage LED (DS702) will initially be red but will turn off quickly as the interface voltage on the FPGA is changed to 1.8V
    • The system ok LED (DS703) will start to flash green constantly. 
    • The power good LED (DS901) will turn on green, this LED might be a bit feint but is ok as long as it is on. 
    • The clock power and devclk_aux LED, both at the top of the board, will turn on. Devclk_aux will only be off if the switch is changed to the external clk setting. 
  • Some setups will note that the fan on the FPGA no longer spins when connected to the FPGA fan header. This issue will not appear for everyone, but for those that do see this behavior, the solution is to connect the fan cable to the fan header on the ADRV9001 daughter card.
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