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Level of DEVCLK_IN signal on EVAL-ADRV9002

Category: Datasheet/Specs

Hello, I would like to experiment with higher frequency of device clock on EVAL-ADRV9002 to evaluate properties of frequency hopping in the mode of retuning. 

What is the appropriate level of clock signal (in dBm) on DEVCLK_IN (J501 SMA connector)? 

Thank you and Regards,
Jakub