ADRV9002 CSSI DDR 4-Lane fails at 15.36Msps

Support,

When selecting an LTE Profile from within TES 0.18.1, I've noticed the Tx data is corrupt when playing out the supplied LTE test vector (CFR_sample_rate_15p36M_bw_10M) over a 4-Lane CMOS DDR SSI configuration.  The behavior was also noted with a simple two-tone Tx vector generated by TES in the Transmit tab and confirmed using the Tx SSI Loopback feature available in the Advanced Features Tab.  The Rx Loopback data matches the transmitted waveform captured on a spectrum analyzer.  The attached images illustrate the expected behavior at 7.68Msps and corrupt data at 15.36Msps.

The issue occurs using both the ZYNQ3 variant of the ZC706 and with a ZCU102 paired with ADRV9001CE_02B fitted with ADRV9002BBCZ (c0) silicon.   

Regards, -ChuckS

  • Hello Chuck,

    It's highly likely that there is just an error with your SSI. Try:

    1. Re-plug the FMC

    2. Restart FPGA and ADRV9001 device

    3. Connect TES, "File" -> " Reset Preferences"

    Step 3 will clear all previously saved SSI FPGA calibration results and re-do the calibration.

    Give this a try and report your progress!

    Best Regards,
    Oisín.

  • Oisin,

    Following your "Reset Preferences" guidance, the following 4 combinations of ADRV9001CE cards and FPGA Carriers fail to operate using CMOS 4-Lane DDR 15.36Msps (Short or Long strobe) using the supplied LTE profile settings with TES 0.18.1;

    1. ZCU102 & W1
    2. ZCU102 & W2
    3. ZYNQ3 & W1
    4. ZYNQ3 & W2

    Each combination of cards listed operate as expected at CMOS 7.68Msps or LVDS 2Lane 15.36Msps.

    Output spectrum noted and S/Ns used during testing