AD9371 Jesd does not sync

Hi,

I m building an application for initializing and configuring AD9371, uising the mykonos api, and the common drivers. 

I followed the procedure described on the headless.c , all initializations seam correct until BBIC JESD Sync Verification.

The xcvr cores initialization is made successfully using the setup functions of the common drivers.

Usign this code, the sysref is detected but the jesd doesn't sync. 

Why doesn´t it sync ?

/*************************************************************************/
/***** Enable SYSREF to Mykonos and BBIC *****/
/*************************************************************************/
/*** < Action: Sends SYSREF Here > ***/
AD9528_setupSYSREF(&ad9528Clock,16,CONTINUOUS,EIGHT_PULSES);
AD9528_requestSysref(&ad9528Clock,1);

/*** < Info: Mykonos is actively transmitting CGS from the RxFramer> ***/

/*** < Info: Mykonos is actively transmitting CGS from the ObsRxFramer> ***/

/*** < Action: Insert User: BBIC JESD Sync Verification Code Here > ***/
if(jesd_status(bbic_rx_jesd)<0){
xil_printf("RX JESD SYNC ERROR\n");
}

if(jesd_status(bbic_rx_os_jesd)<0){
xil_printf("RX OS JESD SYNC ERROR\n");
}

if(jesd_status(bbic_tx_jesd)<0){
xil_printf("TX JESD SYNC ERROR\n");

Thank you

  • The rx Jesd seems synchronized, reading the FPGA registers. But the Rx_Os and the Tx fail synchronization.

    Any idea how to solve the problem ?  

  • Hello,

    Thank you for your question, however, this is not a product support space. Please post your questions in an applicable product forum. You may use the search field on the home page to understand where you need to post your question.

  • Is there a chance you can help this customer now that I have moved the question?

    Thank you

  •  What is the SYNC status ?  Is it at Logic low or Toggles ?

    How are you configuring JESD on FPGA , Are you using any JESD IP ?

    What is your setup. Is it AD9371 Evaluation board with ZC706 Zynq FPGA board ? If its evaluation board you need not worry about signal integrity issues.

    Please refer below docs on JESD. Refer Page 18 for JESD debugging.

    www.analog.com/media/en/technical.../technical.../JESD204B-Survival-Guide.pdf

    Need to identify where you are struck , In CGS phase or ILAS phase first .

    I am seeing multiple posts from you on same topic , We will follow the discussion here .

  • Thank you for your interest.

    I am using the 2016_r2 hdl realease from analog with the buld configuration for the adrv9371 board to configure the FPGA hardware. The FPGA is a ZC706 Zynq evaluation board.

    This release uses the xilinx JESD IP and the AXI_ADXCVR and UTIL_ADVXCR IP cores from analog for the JESD interface with the ADRV9371 board.

    In order to generate valid profiles for the ADC/DACs on the ad9371 board, as well as a valid JESD profile, I use the analog TES software. After I have the clock rates I am able to configure the adrv9371 board using the API from analog without any problem. I configure the Analog IP cores (the AXI_ADXCVR cores) for each JESD interface for the same rates using the DRP interface. I also initialize other clock generator cores (AXI_CLKGEN IP cores from Analog) to produce 1/40 of the JESD lane rate to feed the JESD IP cores from Xilinx  (this rate is correctly measured by the ADC/DAC core of the AD9371 from Analog vs the AXI interface clock). Finally, I configure the JESD IP cores from Xilinx with the JESD interface characteristics.

    After running the JESD initialization procedure I check the status on the FPGA (reading the Xilinx IP core registers) and ADRV9371 side (using the Analog API). For most rates the TX (FPGA is the Framer, ADRV9371 is the Deframer) initializes correctly but the RX side for both the observation channels and the normal channels will fail link SYNC and the Framers will remain in CGS. For some lane rates I have managed to either move past sync for the observation channels or the normal channels but never both, when the framer moves past link SYNC the ILAS stage will also proceed without any problem (eventually there is one NOT IN TABLE error which is not repeated). However, in these cases, either there is no data on the FPGA side or the data is very strange and insensitive to what is on the receivers.

    I have also run some tests with some strange results:

     - Changing the lane rate for the observation channel lanes in the FPGA impacts the synchronization of the other receivers.

     - Changing the lane rate of the normal receivers will also impact the synchronization of the observation channels.

    This led me to believe that somehow the lanes were badly assign for each JESD IP core, I've used the crossbar on the ADRV9371 board to switch the lanes but this also has not improved the situation.