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AD9375 IMAGE FREQUENCY ISSUE

Category: Software
Product Number: AD9375, ZYNQ ULTRASCALE+MPSoC
Software Version: 2019R2 HDL and No-OS

Hello,

In my custom board I am interfacing AD9375 IC with Zynq Ultrascale plus MPSoC (XCZU11EG-ffvc1156) in the custom board.
I am using 2019R2 version of HDL code and No-OS application.
Trying generate single tone frequency on TX1 with the following settings.
LO : 2500 MHz, MSG : 10 MHz
All other configuration settings are default as given No-OS application of 2019R2
I am able to observe the TX1 output in SA but it has image frequency component along with the actual frequency component, SA output added for reference
In the below screenshot output is observed at Peak1 : 2010Mhz(LO+MSG) Peak2: 1990Mhz(LO-MSG), I have to suppress lower side component(LO-MSG) but I couldn't understand what is the reason for this observation, is it because of improper mixing?? or improper filtering.
Can u please let me know what could be the reason for this observation.

Please wait...
AD9528_initialize Done.
rx_clkgen: MMCM-PLL locked (122880000 Hz)
tx_clkgen: MMCM-PLL locked (122880000 Hz)
rx_os_clkgen: MMCM-PLL locked (122880000 Hz)
MCS successful
CLKPLL locked
AD9371 ARM version 5.2.2
PLLs locked
Calibrations completed successfully
tx_adxcvr: OK (4915200 kHz)
rx_adxcvr: OK (4915200 kHz)
rx_os_adxcvr: OK (4915200 kHz)
RxFramerStatus = 0x20
DeframerStatus = 0x68
rx_jesd status:
        Link is enabled
        Measured Link Clock: 122.881 MHz
        Reported Link Clock: 122.880 MHz
        Lane rate: 4915.200 MHz
        Lane rate / 40: 122.880 MHz
        LMFC rate: 3.840 MHz
        Link status: DATA
        SYSREF captured: Yes
        SYSREF alignment error: No
rx_jesd lane 0 status:
Errors: 0
        CGS state: DATA
        Initial Frame Synchronization: No
rx_jesd lane 1 status:
Errors: 0
        CGS state: DATA
        Initial Frame Synchronization: No
tx_jesd status:
        Link is enabled
        Measured Link Clock: 122.881 MHz
        Reported Link Clock: 122.880 MHz
        Lane rate: 4915.200 MHz
        Lane rate / 40: 122.880 MHz
        LMFC rate: 7.680 MHz
        SYNC~: deasserted
        Link status: DATA
        SYSREF captured: Yes
        SYSREF alignment error: No
rx_os_jesd status:
        Link is enabled
        Measured Link Clock: 122.881 MHz
        Reported Link Clock: 122.880 MHz
        Lane rate: 4915.200 MHz
        Lane rate / 40: 122.880 MHz
        LMFC rate: 7.680 MHz
        Link status: DATA
        SYSREF captured: Yes
        SYSREF alignment error: No
rx_os_jesd lane 0 status:
Errors: 0
        CGS state: DATA
        Initial Frame Synchronization: Yes
        Lane Latency: 1 Multi-frames and 60 Octets
        Initial Lane Alignment Sequence: Yes
        DID: 0, BID: 0, LID: 0, L: 2, SCR: 1, F: 2
        K: 32, M: 2, N: 16, CS: 0, N': 16, S: 1, HD: 0
        FCHK: 0x43, CF: 0
        ADJCNT: 0, PHADJ: 0, ADJDIR: 0, JESDV: 1, SUBCLASS: 1
        FC: 4915200 kHz
rx_os_jesd lane 1 status:
Errors: 0
        CGS state: DATA
        Initial Frame Synchronization: Yes
        Lane Latency: 1 Multi-frames and 61 Octets
        Initial Lane Alignment Sequence: Yes
        DID: 0, BID: 0, LID: 1, L: 2, SCR: 1, F: 2
        K: 32, M: 2, N: 16, CS: 0, N': 16, S: 1, HD: 0
        FCHK: 0x44, CF: 0
        ADJCNT: 0, PHADJ: 0, ADJDIR: 0, JESDV: 1, SUBCLASS: 1
        FC: 4915200 kHz
tx_dac: Successfully initialized (245761108 Hz)
rx_adc: Successfully initialized (122875976 Hz)
rx_obs_adc: Successfully initialized (245751953 Hz)
Done

Note :
1. Added the COM port log for reference
2. To confirm weather RF path is working or not I have checked with NCO and output is good (Observed only actual frequency component)
3. EVM (ZCU102+ADRV9375-W) is working fine with same setting

Regards,

Naveen Kumar