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AD9375 jesd lane error

Hello,

I am using the AD9375 Evaluation board(ADRV9375-W/PCBZ) with ZC-706 for my project
Here I'm facing some issues while debugging and the issues were mentioned below:
JESD204 interface status:
  • while checking the jesd204 interface status by the function axi_jesd204_rx_laneinfo_read( ) sometimes get "error: 1" should I care about the errors? I attached a file

Please wait...
IF : AD9528_ADDR_STATUS_READBACK0(Reg508) : f2
WARNING: AD9528_initialize() issues. Possible cause: REF_CLK not connected.
rx_clkgen: MMCM-PLL locked (122880000 Hz)
tx_clkgen: MMCM-PLL locked (122880000 Hz)
rx_os_clkgen: MMCM-PLL locked (122880000 Hz)
MCS successful
CLKPLL locked
AD9371 ARM version 5.2.2
PLLs locked
Calibrations completed successfully
tx_adxcvr: OK (4915200 kHz)
rx_adxcvr: OK (4915200 kHz)
rx_os_adxcvr: OK (4915200 kHz)
rx_jesd status:
        Link is enabled
        Measured Link Clock: 122.874 MHz
        Reported Link Clock: 122.880 MHz
        Lane rate: 4915.200 MHz
        Lane rate / 40: 122.880 MHz
        LMFC rate: 3.840 MHz
        Link status: DATA
        SYSREF captured: Yes
        SYSREF alignment error: No
rx_jesd lane 0 status:
Errors: 0
        CGS state: DATA
        Initial Frame Synchronization: Yes
        Lane Latency: 1 Multi-frames and 73 Octets
        Initial Lane Alignment Sequence: Yes
        DID: 0, BID: 0, LID: 0, L: 2, SCR: 1, F: 4
        K: 32, M: 4, N: 16, CS: 0, N': 16, S: 1, HD: 0
        FCHK: 0x47, CF: 0
        ADJCNT: 0, PHADJ: 0, ADJDIR: 0, JESDV: 1, SUBCLASS: 1
        FC: 4915200 kHz
rx_jesd lane 1 status:
Errors: 1
        CGS state: DATA
        Initial Frame Synchronization: Yes
        Lane Latency: 1 Multi-frames and 73 Octets
        Initial Lane Alignment Sequence: Yes
        DID: 0, BID: 0, LID: 1, L: 2, SCR: 1, F: 4
        K: 32, M: 4, N: 16, CS: 0, N': 16, S: 1, HD: 0
        FCHK: 0x48, CF: 0
        ADJCNT: 0, PHADJ: 0, ADJDIR: 0, JESDV: 1, SUBCLASS: 1
        FC: 4915200 kHz
tx_jesd status:
        Link is enabled
        Measured Link Clock: 122.876 MHz
        Reported Link Clock: 122.880 MHz
        Lane rate: 4915.200 MHz
        Lane rate / 40: 122.880 MHz
        LMFC rate: 7.680 MHz
        SYNC~: deasserted
        Link status: DATA
        SYSREF captured: Yes
        SYSREF alignment error: No
rx_os_jesd status:
        Link is enabled
        Measured Link Clock: 122.874 MHz
        Reported Link Clock: 122.880 MHz
        Lane rate: 4915.200 MHz
        Lane rate / 40: 122.880 MHz
        LMFC rate: 7.680 MHz
        Link status: DATA
        SYSREF captured: Yes
        SYSREF alignment error: No
rx_os_jesd lane 0 status:
Errors: 0
        CGS state: DATA
        Initial Frame Synchronization: Yes
        Lane Latency: 2 Multi-frames and 5 Octets
        Initial Lane Alignment Sequence: Yes
        DID: 0, BID: 0, LID: 0, L: 2, SCR: 1, F: 2
        K: 32, M: 2, N: 16, CS: 0, N': 16, S: 1, HD: 0
        FCHK: 0x43, CF: 0
        ADJCNT: 0, PHADJ: 0, ADJDIR: 0, JESDV: 1, SUBCLASS: 1
        FC: 4915200 kHz
rx_os_jesd lane 1 status:
Errors: 0
        CGS state: DATA
        Initial Frame Synchronization: Yes
        Lane Latency: 2 Multi-frames and 6 Octets
        Initial Lane Alignment Sequence: Yes
        DID: 0, BID: 0, LID: 1, L: 2, SCR: 1, F: 2
        K: 32, M: 2, N: 16, CS: 0, N': 16, S: 1, HD: 0
        FCHK: 0x44, CF: 0
        ADJCNT: 0, PHADJ: 0, ADJDIR: 0, JESDV: 1, SUBCLASS: 1
        FC: 4915200 kHz
tx_dac: Successfully initialized (245751953 Hz)
rx_adc: Successfully initialized (122874450 Hz)
rx_obs_adc: Successfully initialized (245748901 Hz)
Done

  • I checked the Framer Status = 0x3E and  deframer Status = 0x28, and 
  • when I executed the function MYKONOS_jesd204bIlasCheck() I got mismatch value is 0x0 So, this is expected or not ?
    uint16_t mismatch;
    mykError = MYKONOS_jesd204bIlasCheck(&mykDevice, &mismatch);
    if (mykError == MYKONOS_ERR_OK)
    printf("mismatch = 0x%x\n", mismatch);

AD9375 and FPGA Clock:
  • While running the code AD9375 and observing that clock mismatch, means that the AD9375 clock and FPGA-related clock are different. So this is expected or not?
  •  AD9375:
    • tx_clkgen: MMCM-PLL locked (122880000 Hz)
    • rx_clkgen: MMCM-PLL locked (122880000 Hz)
    • rx_os_clkgen: MMCM-PLL locked (122880000 Hz)
  • FPGA:
    • tx_dac: Successfully initialized (245751953 Hz)
    • rx_adc: Successfully initialized (122874450 Hz)
    • rx_obs_adc: Successfully initialized (245748901 Hz)