I'm dealing with AD9371 initialization process using a host Linux PC and only one AD9371 chip is used. But something went wrong in MultiChip Sysc step. The mcsStatus == 0x00 always.
I sent 6 SYSREF pluses between first and second time calls of MYKONOS_enableMultichipSync() while also disable the SYSREF before the first time. My SYSREF generator is AD9528 and follow the recommended frequency 120kHz. This frequency is correct, I verified it according to UG-992 requirement: The frequency of the SYSREF pulse train must be a submultiple of the JESD204B local multiframe counter (LMFC) rate.
What could I do to debug this problem? I can hardly see anything about MultiChip Sysc operation from the source code, there is only a spi write commend to start the process in that API function. The MYKONOS_initialize() returns OK, the CLKPLL has locked, everything is OK before multichip sysc step. Are there anything else I need to do except MYKONOS_initialize() and Check CLKPLL before MultiChip Sysc?
Also one thing I'm not sure is that I do not download JESD204B IP core in to my FPGA before the initialization process. I don't know whether this is the cause of the fail of MutiChip Sync?
Change some words
[edited by: xiaoyoumin at 8:03 AM (GMT -5) on 19 Nov 2020]