Problem in AD9371 MultiChip Sysc

Hi,

I'm dealing with AD9371 initialization process using a host Linux PC and only one AD9371 chip is used. But something went wrong in MultiChip Sysc step. The mcsStatus == 0x00 always.

I sent 6 SYSREF pluses between first and second time calls of MYKONOS_enableMultichipSync() while also disable the SYSREF before the first time. My SYSREF generator is AD9528 and follow the recommended frequency 120kHz. This frequency is correct, I verified it according to UG-992 requirement: The frequency of the SYSREF pulse train must be a submultiple of the JESD204B local multiframe counter (LMFC) rate. 

What could I do to debug this problem? I can hardly see anything about MultiChip Sysc operation from the source code, there is only a spi write commend to start the process in that API function. The MYKONOS_initialize() returns OK, the CLKPLL has locked, everything is OK before multichip sysc step. Are there anything else I need to do except MYKONOS_initialize() and Check CLKPLL before MultiChip Sysc?

Also one thing I'm not sure is that I do not download JESD204B IP core in to my FPGA before the initialization process. I don't know whether this is the cause of the fail of MutiChip Sync?



Change some words
[edited by: xiaoyoumin at 8:03 AM (GMT -5) on 19 Nov 2020]
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  • 0
    •  Analog Employees 
    on Nov 23, 2020 9:05 AM in reply to xiaoyoumin

    So you have to integrate the corresponding JESD IP core into the FPGA for the chip to initialize successfully.

  • Thank you so much for your help! But does this MultiChip Sysc step require JESD IP core? I didn’t find any communication between AD9371 and FPGA using JESD204B interface from UG. Could you give me some detailed information about the communications between AD9371 and FPGA in the multichip sync operation using JESD204B interface?

  • 0
    •  Analog Employees 
    on Nov 24, 2020 8:59 AM in reply to xiaoyoumin

    Yes you have to add JESD in FPGA for MCS to work and you will not see any communication between FPGA and the board without that. 

    From UG:

    Perform multichip synchronization. Send at least two initial SYSREF rising edges for multichip sync between multiple devices. For proper synchronization, the same SYSREF pulses must be seen at each AD9371 during the same device clock cycle. If only a single AD9371 is used, this step is still required to ensure JESD204B deterministic latency. For proper operation, it is recommended to disable the SYSREF, enable multichip synchronization, then reenable SYSREF. SYSREF may either be a single pulse or free running..

    Refer to the "LINK ESTABLISHMENT" section in UG.