I am trying to set up the AD9371 on a custom board and am running into errors. I used the Filter wizard v1.8 to create a custom profile and imported that into the TES software tool to export the c files for API set up. When I run it goes error free until I get to the call to MYKONOS_setRfPllFrequency with TX_PLL as a parameter. This function call returns the error MYKONOS_ERR_SETRFPLL_ARMERROR. Stepping into the call it is the call to MYKONOS_waitArmCmdStatus that returns an error of MYKONOS_ERR_ARMCMDSTATUS_ARMERROR with a value for cmdStatusByte of 0x8. A previous call to MYKONOS_setRfPllFrequency with RX_PLL as a parameter succeeds.
Please make sure that you follow the "RF PLL FREQUENCY CHANGE PROCEDURE" given in UG-992.
Are you using No-OS or Linux driver?
Can you please share the sequence you are following for RF PLL set?
I realized I wasn't using the latest version of the filter wizard so I downloaded v1.10 and had the same results
Make sure that you are using the latest version of the TES GUI from the below link:
Are you able to program the chip successfully with the custom profile using TES GUI?
My profile doesn't use a clock that is compatible with the eval board so I can't load it using the TES GUI. I am using the latest
Can you please check whether the AD9528 device programmed properly and outputs the intended frequency at the reference clock input of AD9371?
This is a custom board so the clock isn't being generated by an ad9528 but I have verified that we do indeed have the specified 100MHz clock at the reference clock input to the ad9371
Can you please share the init files that you generated from TES GUI?
What is the version of the HDL and No-oS driver you are using?
Did you check with any other device clock and other LO frequency?
If you are able to configure the Rx PLL successfully can you please read back the lock status?
Are you able to configure the sniffer PLL?
I checked multiple LO frequencies.
The Sniffer LO set up fails with the same error
No-OS version is the latest Github commit
Not sure what HDL version you are refering to since this is a custom board but I haven't even made it to the part where it needs to talk to the FPGA so that seems irrelevant
value of pllLockStatus after attempting to set all 3 PLLs is 0x7
I'm not sure how to attach a file without linking to it which I can't do so it will be pasted into a separate comment