AD9528 clock not synchronized

Did you check the clock setting tab in the TES GUI? Is the REF_CLK set to 30.72MHz there?

I have the same issue, I checked the Ref Clock of AD9528 and it is 30.72MHz. Please let me know if other configuration are needed to be checked. 

Thanks

Did you check the REF_Clk parameter in GUI? Is it set to 30.72MHz?

I did check that one as well and it was right.

I realize while TES is running, I cannot reset FPGA. If FPGA has been reset, I need to also reset TES otherwise I will get this error.

Thanks 

Are you still having the issue?

If you are restarting the board without disconnecting the TES GUI from the board this issue can happen.

No issue anymore. Thanks for your help.