Error waiting for CLKPLL CP Cal done and CLKPLL Lock

Hi,

I have a design in which I've modified the adrv9371x.kcu105 design where I added a second master to the internal AXI CPU interconnect. This master is a PCI-E/AXI Bridge that we've used and proven before in a previous adaption of an AD9361 reference design. In this modified design, a 125MHz PCI-E clock is used in place of the 100MHz clock for the Microblaze/AXI Lite clock. Even with this modification, the Microblaze can still be programmed with the no-OS code and can fully configure the AD9528 and AD9371 and I have a tool to verify that the IQ looks good.

The goal is to take the no-OS software and run it locally on an x86 PC and configure the AD9528 and the AD9371 over PCI-E. I've done significant debugging, including confirming that every write (be it either internal FPGA writes/reads or SPI writes/reads) are occurring correctly by doing write/readback tests when running the no-OS software. Additionally, the no-OS software proceeds through quite a few of its built-in software checks (e.g. AD9528 check that register 0x508 has correct status value, etc.), but I'm always getting a timeout at the following line in mykonos.c when running over PCI-E

    /* Wait for CLKPLL CP Cal done and CLKPLL Lock  or throw error message */
    CMB_wait_ms(500);
    retVal = MYKONOS_waitForEvent(device, CLKPLLCP, 1000000);
    if (retVal != MYKONOS_ERR_OK)
    {
        return retVal;
    }

I can define the macro MYK_CALS_DONE_SWDEBUG, but then the software just proceeds until it gets to "CLKPLL not locked (0xe)".

Without having an AD9371 register map I'm not sure what to do with this info or how to proceed. I keep doing I/O checks (e.g. checked GPIO and SPI including chip selects via Chipscope) and comparing the Microblaze transactions to the PCI-E but I'm not seeing any obvious difference.

Any advice is greatly appreciated.