I checked that ADS9-v2EBZ has "Twenty (20) 28Gbps transceivers supported by one (1) FMC+ connector" and HMC Gen2DRAM. Does that mean it can write to the DRAM at a speed of 20×28Gbit/s = 560Gbit/s (or 70GByte/s)?
While it is correct that the board has twenty 28 Gbps transceivers the HMC DRAM cannot run at 70 GByte/s. This is because data moved over any memory interface takes a hit in efficiency. We ran some experiments, and these are the numbers that we got using the ADS9v2-EBZ board and our FPGA design which stripes data across two HMC memory modules. It would be half of this if the user used one HMC memory module.
only read: ~51 GByte/s
posted write and read: ~37.4 GByte/s write, 37.4 GByte/s read
only posted write: ~42 GByte/s
How much memory does the HMC Gen2 DRAM on the ADS9v2-EBZ board can I really access?
The ADS9v2 has 4 HMC modules. Each module is a 2 GByte module. The modules are connected to where 2 have direct access to the FPGA and the 2 others can be accessed through chaining. The user could potentially access 8 GByte of memory but using the chaining path comes at the cost of lower throughput in addition to the complexity.