Post Go back to editing

Initilization Problem When Bypassing Channelizer Path

Category: Software

Hi, I am trying to test bypassing the channelizer path on AD9081 (Channelizer Interpolation Factor (N) = 1) in order to provide maximum data rate (1500 MSPS) limitation. However, I encountered an initilization problem. I can not see any spectrum when I debug it. After I programmed it, I read IRQ_STATUS_0 (0x0026) register different (DAC IRQ STATUS = 0xf043000000) than I expected on the serial terminal. I also see that it prints IRQ _Status0 = 0x0, ad9081_multichip_sync: 2  and ad9081_multichip_sync: 3. When I use interpolation factor (N > 1), I read this register as (DAC IRQ STATUS = 0xf043000040). I do not know what is the problem. Do you have any recommendation about this problem to solve it. 

  • Hello,

    Difficult to debug based on the information above.  

    Are you using ACE software with ADI's evaluation board/ADS9-V2 FPGA board?  If so...............can you save and send us the configuration file along with the preferred IQ data rate.  Also.................can you send the "log file" that can be downloaded showing  the API calls and assoiciated SPI writes used to configure the device.

  • Hello,
    I am not using the ADS9-V2, I am using the NO-OS project from the branch 2021_R1. Should I share the log from this?
    Btw I receive this error only when I keep my N =1.

  • Moving to Mixer-Signal Front End (MxFE).

  • Hello,

    When you say you are changing your N value do you mean you are updating the AD9081_TX_CHAN_INTERPOLATION definition in app_config.h? Is this the only change you are making between the two builds?

  • If you change the interpolation you will also need to change either the AD9081_DAC_FREQUENCY value or your incoming datarate from the ADS9 FPGA, since the DAC output rate needs to be equal to the incoming datarate x total interpolation. For example, in the original project file the TX main/chan interpolation is 6x/8x and the DAC frequency is 12GHz, so your incoming data rate would be 250MHz. If you change the interpolation to 1x/8x and maintain the same FPGA datarate you have to drop the DAC frequency by 6x, to 2GHz. If the rates do not match you will not see the expected output. 

    Let me know if updating that parameter helps.

  • I understood what you said. Actually, data rate is 500 MSPS and DAC frequency is 4 GHz before changing channelizer interpolation value to 1. I want to keep the DAC frequency at 4 GHz and interpolation factor at 8. Therefore, when I change from 4x2 total interpolation to 8x1 as main and channelizer respectively for JESD 6 configuration, should the data rate be lower than 500 MSPS? I know I have a maximum data rate limitation (1500 MSPS) for the channelizer path. Does this also apply to the main path?

  • 500MSPS with 8x1x main/channel interpolation and a 4GHz DAC rate should work. The 1500MSPS datarate limit on the channels is due to the speed of the summing node between the channels and main DAC datapath, and does not apply to the main datapath itself. However, 1x channel interpolation bypasses the channel datapaths altogether, so you don't need to worry about the summing node limitation. In this case you are just sending your I/Q data directly into the main datapath without any fine NCO shifts. The only limitations to worry about in this case are the maximum jesd lane rate (24.75Gbps for JESD204C and 15.5Gbps for JESD204B) and the DAC min/max update rates (2.91/12GHz). Your lane rate of 10Gbps and Fdac of 4GHz are well within these limits.

  • Hi Kberry, thank you for responding back,
    The main problem now is that when setting the channel interpolation to 1 as mentioned in the original post is that I have a different IRQ Status when I bypass it as compared to when I do not bypass it. Also setting the channel interpolation to 1 makes it to do multichip synchronization which it should not? Why is that so? Should I ignore it? or is something wrong that requires to be fixed?


  • Are you seeing an output tone as expected when bypassing the channelizers with N=1? If the IRQ status ends 0x40 it means the JESD receiver is ready; 0x00 means it is not ready. When it is not ready, the code will run multichip sync steps 2 & 3, which toggle the JESD receiver enable. If there are any issues with the jesd or clocking parameters (dac clock, interp, as discussed) then link would not be ready for data. However if you are seeing the jesd link working with N=1 but still getting this 0x00 status that is curious.