I would like to confirm if I am doing the right thing, with regard to the DAC transport layer in AD9081 HDL design.
I have generated my JESD parameters from the JESD helper tool provided by analog devices. Which are as follows: M=2, L=2, F=2, S=1, N=NP=16, K=32. The HDL design generated from this parameters provided generate a JESD transport layer where the width of the dac_ddata is 64 bits. From my understanding from this link , The data entering from upack to the transport layer should be of this format: dac_data0 = [I1, I0] and dac_data1 = [Q1, Q0] assuming my I and Q are of 16bits each. dac_data0 and dac_data1 are concatenated and form dac_ddata as [Q1, Q0, I1, I0]. Would this be correct or should it be in another format?
Additonal information with regard to my design:
I am using mod mux configuration 3B where I frames are directed to DAC0 and Q frames are directed to DAC1. I only use CDUC0 and FDUC0.