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How do I calculate the loop filter value for AD9081?

Category: Hardware
Product Number: AD9081

Hi

I would like to make the VCO output 12GHz by setting AD9081 as below.

Fin => 100MHz, Mvco => 5, Nvco => 24, R => 1

However, it is monitored that SLOW LOCK does not work at all and FAST LOCK continues to unravel.

Do you have any calculation or reference materials to solve this problem?

Thank you!

  • Hello,

    The next release of ADIsimPLL (version 5.60.02) will include a model of the MxFE on-chip PLL Syn.  This release is scheduled within next 3 weeks and can be downloaded from following link.    ADIsimPLL | Design Center | Analog Devices
    This software tool will allow one to optimize the loop-filter and charge pump settings for a given FREF and FDAC requirement.

    With regard to your  question, the following comments can be made:
    -The PLL R, M, N and L settings are set via software API based on FREF, FDAC, and FADC parameters.

    -As figure 11 in UG1578 shows.............best phase noise is achieved when using a higher PFD frequency for the PLL.  Using an FREF of 100 MHz (which results in PFD freq also of 100 MHz with R=1) results in poor phase noise characteristics below 1 MHz vs selecting a higher PFD.

    -If one is using the AD9081 ACE Plug-in GUI (with HMC7044 clock generator)............suggest setting the "Chip Ref Clock" setting to 500 MHz instead.

    Regards

  • Hi  ,

    I downloaded the newest version of ADIsimPLL (5.50) whose welcome message said the AD9081 was supported. I can't seem to find the AD9081 as a choice in the loop filter design dropdown menu though. Is this released?

    • Picture of support message
    • Picture of drop-down menu (can't find AD9081)