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Is AD9081's "device clock" CLKIN or DACCLK when supporting Subclass 1?

Category: Datasheet/Specs
Product Number: AD9081
Software Version: N/A

I'd like to support deterministic latency through Subclass 1 with the AD9081, and that requires a tight relationship between a "device clock" and SYSREF. When using the AD9081's on-chip PLL, I'm not sure if "device clock" is the ~MHz reference on CLKINP/N or the ~GHz DACCLK after the PLL. The user guide sometimes seems to imply both, and I've put the conflicting sections below.

Is the "device clock" that SYSREF is timed to the reference coming in on the CLKINP/N pins or the DACCLK after the on-chip PLL? 

  • A few figures in the user guide seem to imply SYSREF is timed with DACCLK so that "device clock" = CLK = DACCLK. DACCLK is what clocks the SERDES blocks
    • Pg 7 of the user guide
    • Pg 26 of the user guide
  • However, the user guide also seems imply SYSREF is timed to the lower frequency reference on the CLKINP/N pins. So "device clock" != DACCLK
    • Pg 27 of the user guide
    • Pg 30 of the user guide describing the SYSREF Setup and Hold Time Monitor, which helps SYSREF meet timing with respect to CLKINP/N (not DACCLK) 
    • Pg 57 of the user guide referencing device clock as CLKIN+/- 


Edit- change category to "Datasheet/Specs"
[edited by: youngpines at 11:12 PM (GMT -4) on 14 Jun 2022]