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Unable to configure ADC using API in VCU118 ad9082, UG1578 register information missing in table 195.

Category: Software
Product Number: vcu118, ad9082
Software Version: api v1.2.2 commit 5b813df for ad9082

I am using VCU118 board + AD9082 with setup as shown in link wiki.analog.com/.../microblaze but with AD9082 board.

The aim is to bring up the two ADC of 9082 for 2GHz bandwidth and transmit the sampled data onto JESD204C.

I am refering to UG1578 and API (api v1.2.2 commit 5b813df for ad9082) for my development.

I have integrated the API source with my HAL code for SPI access (spi_xfer) and tx_en_pin_ctrl.

Calling the following functions as per "Figure 1. System High Level API Calls Overview" of "AD9081 / AD9082 / AD9986 / AD9988 / AD9207 / AD9177 API Specification, Integration and Porting Guide. Rev 1.2.2"

/////////////////////////////////////////////////////////////////////////////////////
///////////////////////////   Populated structure details ///////////////////////////
/////////////////////////////////////////////////////////////////////////////////////
	print("init_adc_api_Structure\r\n");
	adcDev.hal_info.user_data = &adcUserData; /*!< Pointer to connect customer data related to this device */
	adcDev.hal_info.sdo = SPI_SDO; /*!< SPI interface 3/4 wire mode configuration */
	adcDev.hal_info.msb = SPI_MSB_FIRST; //SPI_MSB_LAST /*!< SPI interface MSB/LSB bit order configuration */
	adcDev.hal_info.addr_inc = SPI_ADDR_DEC_AUTO; //SPI_ADDR_DEC_AUTO /*!< SPI interface address increment configuration */

	adcDev.hal_info.spi_xfer = hal_spi; /*!< Function pointer to hal spi access function */
	adcDev.hal_info.delay_us = hal_delay_us; /*!< Function pointer to hal delay function */
	adcDev.hal_info.hw_open = hal_hw_open; /*!< Function pointer to hal initialization function */
	adcDev.hal_info.hw_close = hal_hw_close; /*!< Function pointer to hal de-initialization function */
	adcDev.hal_info.log_write = hal_log_write; /*!< Function pointer to hal log write function */
	adcDev.hal_info.tx_en_pin_ctrl = hal_tx_en_pin_ctrl; /*!< Function pointer to hal tx_enable pin control function */
	adcDev.hal_info.reset_pin_ctrl = hal_pd_stby_pin_ctrl; /*!< Function pointer to hal reset# pin control function */

	/* YTBD
	 * ref = lane_rate/66*/
	adcDev.dev_info.dev_freq_hz = (AD9082_REF_CLK_FREQ_HZ_MIN
			+ AD9082_REF_CLK_FREQ_HZ_MAX) / 2; //(uint64_t) (250 * 1000 * 1000); /*!< Device clock frequency in Hz */
	adcDev.dev_info.dac_freq_hz = 4400000000ULL; // (AD9082_DAC_CLK_FREQ_HZ_MIN
	//+ AD9082_DAC_CLK_FREQ_HZ_MAX) / 2; //(uint64_t) (0); /*!< DAC clock frequency in Hz */
	adcDev.dev_info.adc_freq_hz = 4400000000ULL;//(AD9082_ADC_CLK_FREQ_HZ_MIN
	//+ AD9082_ADC_CLK_FREQ_HZ_MAX) / 2; //(uint64_t) (4400 * 1000 * 1000); /*!< ADC clock frequency in Hz */
	adcDev.dev_info.dev_rev = 3; /*!< Device revision, 0:r0, 1:r1, 2:r1r, 3:r2 */

	adcDev.serdes_info.des_settings.boost_mask = 0; /*Calibration boost mode enable Mask,Set per Lane,Enable (Set to 1) if the channels insertion loss is greater than 10 dB*/
	adcDev.serdes_info.des_settings.invert_mask = 0; /*Lane Inversion Mask*/

	/*Equaliser CTLE Filter Selection, Range 0 - 4, based on Jesd IL, Pick lower setting for Higher Insertion loss*/
	adcDev.serdes_info.des_settings.ctle_filter[0] = 0;
	adcDev.serdes_info.des_settings.ctle_filter[1] = 0;
	adcDev.serdes_info.des_settings.ctle_filter[2] = 0;
	adcDev.serdes_info.des_settings.ctle_filter[3] = 0;
	adcDev.serdes_info.des_settings.ctle_filter[4] = 0;
	adcDev.serdes_info.des_settings.ctle_filter[5] = 0;
	adcDev.serdes_info.des_settings.ctle_filter[6] = 0;
	adcDev.serdes_info.des_settings.ctle_filter[7] = 0;

	/*Deserialise Lane Mapping, Map Virtual Converter to Physical Lane, index is logical lane, value is physical lane*/
	adcDev.serdes_info.des_settings.lane_mapping[0][0] = 0;
	adcDev.serdes_info.des_settings.lane_mapping[0][1] = 1;
	adcDev.serdes_info.des_settings.lane_mapping[0][2] = 2;
	adcDev.serdes_info.des_settings.lane_mapping[0][3] = 3;
	adcDev.serdes_info.des_settings.lane_mapping[0][4] = 4;
	adcDev.serdes_info.des_settings.lane_mapping[0][5] = 5;
	adcDev.serdes_info.des_settings.lane_mapping[0][6] = 6;
	adcDev.serdes_info.des_settings.lane_mapping[0][7] = 7;

	adcDev.serdes_info.des_settings.lane_mapping[1][0] = 0;
	adcDev.serdes_info.des_settings.lane_mapping[1][1] = 1;
	adcDev.serdes_info.des_settings.lane_mapping[1][2] = 2;
	adcDev.serdes_info.des_settings.lane_mapping[1][3] = 3;
	adcDev.serdes_info.des_settings.lane_mapping[1][4] = 4;
	adcDev.serdes_info.des_settings.lane_mapping[1][5] = 5;
	adcDev.serdes_info.des_settings.lane_mapping[1][6] = 6;
	adcDev.serdes_info.des_settings.lane_mapping[1][7] = 7;

	adcDev.serdes_info.ser_settings.lane_settings[0].swing_setting =
			AD9082_SER_SWING_1000;
	adcDev.serdes_info.ser_settings.lane_settings[0].pre_emp_setting =
			AD9082_SER_PRE_EMP_0DB;
	adcDev.serdes_info.ser_settings.lane_settings[0].post_emp_setting =
			AD9082_SER_POST_EMP_0DB;

	adcDev.serdes_info.ser_settings.lane_settings[1].swing_setting =
			AD9082_SER_SWING_1000;
	adcDev.serdes_info.ser_settings.lane_settings[1].pre_emp_setting =
			AD9082_SER_PRE_EMP_0DB;
	adcDev.serdes_info.ser_settings.lane_settings[1].post_emp_setting =
			AD9082_SER_POST_EMP_0DB;

	adcDev.serdes_info.ser_settings.lane_settings[2].swing_setting =
			AD9082_SER_SWING_1000;
	adcDev.serdes_info.ser_settings.lane_settings[2].pre_emp_setting =
			AD9082_SER_PRE_EMP_0DB;
	adcDev.serdes_info.ser_settings.lane_settings[2].post_emp_setting =
			AD9082_SER_POST_EMP_0DB;

	adcDev.serdes_info.ser_settings.lane_settings[3].swing_setting =
			AD9082_SER_SWING_1000;
	adcDev.serdes_info.ser_settings.lane_settings[3].pre_emp_setting =
			AD9082_SER_PRE_EMP_0DB;
	adcDev.serdes_info.ser_settings.lane_settings[3].post_emp_setting =
			AD9082_SER_POST_EMP_0DB;

	adcDev.serdes_info.ser_settings.lane_settings[4].swing_setting =
			AD9082_SER_SWING_1000;
	adcDev.serdes_info.ser_settings.lane_settings[4].pre_emp_setting =
			AD9082_SER_PRE_EMP_0DB;
	adcDev.serdes_info.ser_settings.lane_settings[4].post_emp_setting =
			AD9082_SER_POST_EMP_0DB;

	adcDev.serdes_info.ser_settings.lane_settings[5].swing_setting =
			AD9082_SER_SWING_1000;
	adcDev.serdes_info.ser_settings.lane_settings[5].pre_emp_setting =
			AD9082_SER_PRE_EMP_0DB;
	adcDev.serdes_info.ser_settings.lane_settings[5].post_emp_setting =
			AD9082_SER_POST_EMP_0DB;

	adcDev.serdes_info.ser_settings.lane_settings[6].swing_setting =
			AD9082_SER_SWING_1000;
	adcDev.serdes_info.ser_settings.lane_settings[6].pre_emp_setting =
			AD9082_SER_PRE_EMP_0DB;
	adcDev.serdes_info.ser_settings.lane_settings[6].post_emp_setting =
			AD9082_SER_POST_EMP_0DB;

	adcDev.serdes_info.ser_settings.lane_settings[7].swing_setting =
			AD9082_SER_SWING_1000;
	adcDev.serdes_info.ser_settings.lane_settings[7].pre_emp_setting =
			AD9082_SER_PRE_EMP_0DB;
	adcDev.serdes_info.ser_settings.lane_settings[7].post_emp_setting =
			AD9082_SER_POST_EMP_0DB;
			
			
	jesdParam[0].jesd_l = 8; /*!< No of lanes */
	jesdParam[0].jesd_f = 2; /*!< No of octets in a frame */
	jesdParam[0].jesd_m = 2; /*!< No of converters */
	jesdParam[0].jesd_s = 4; /*!< No of samples */
	jesdParam[0].jesd_hd = 0; /*!< High Density */
	jesdParam[0].jesd_k = 128; /*!< No of frames for a multi-frame */
	jesdParam[0].jesd_n = 16; /*!< Converter resolution */
	jesdParam[0].jesd_np = 16; /*!< Bit packing sample */
	jesdParam[0].jesd_cf = 0; /*!< Parameter CF */
	jesdParam[0].jesd_cs = 0; /*!< Parameter CS */
	jesdParam[0].jesd_did = 0; /*!< Device ID DID */
	jesdParam[0].jesd_bid = 0; /*!< Bank ID.  BID */
	jesdParam[0].jesd_lid0 = 0; /*!< Lane ID for lane0 */
	jesdParam[0].jesd_subclass = 1; /*!< Subclass */
	jesdParam[0].jesd_scr = 1; /*!< Scramble enable */
	jesdParam[0].jesd_duallink = 0; /*!< Link mode (single/dual) */
	jesdParam[0].jesd_jesdv = 2; /*!< Version (0:204A, 1:204B, 2:204C) */
	jesdParam[0].jesd_mode_id = 0; /*!< JESD mode ID */
	jesdParam[0].jesd_mode_c2r_en = 0; /*!< JESD mode C2R enable */
	jesdParam[0].jesd_mode_s_sel = 0; /*!< JESD mode S value */

	jesdParam[1].jesd_l = 8; /*!< No of lanes */
	jesdParam[1].jesd_f = 2; /*!< No of octets in a frame */
	jesdParam[1].jesd_m = 2; /*!< No of converters */
	jesdParam[1].jesd_s = 4; /*!< No of samples */
	jesdParam[1].jesd_hd = 0; /*!< High Density */
	jesdParam[1].jesd_k = 128; /*!< No of frames for a multi-frame */
	jesdParam[1].jesd_n = 16; /*!< Converter resolution */
	jesdParam[1].jesd_np = 16; /*!< Bit packing sample */
	jesdParam[1].jesd_cf = 0; /*!< Parameter CF */
	jesdParam[1].jesd_cs = 0; /*!< Parameter CS */
	jesdParam[1].jesd_did = 0; /*!< Device ID DID */
	jesdParam[1].jesd_bid = 0; /*!< Bank ID.  BID */
	jesdParam[1].jesd_lid0 = 0; /*!< Lane ID for lane0 */
	jesdParam[1].jesd_subclass = 1; /*!< Subclass */
	jesdParam[1].jesd_scr = 1; /*!< Scramble enable */
	jesdParam[1].jesd_duallink = 0; /*!< Link mode (single/dual) */
	jesdParam[1].jesd_jesdv = 2; /*!< Version (0:204A, 1:204B, 2:204C) */
	jesdParam[1].jesd_mode_id = 0; /*!< JESD mode ID */
	jesdParam[1].jesd_mode_c2r_en = 0; /*!< JESD mode C2R enable */
	jesdParam[1].jesd_mode_s_sel = 0; /*!< JESD mode S value */

///////////////////////////////////////////////////////////////////////////////////////

//--------------------------- CODE SNIPPET -------------------------------------
	err = adi_ad9082_device_api_revision_get(device, &rev_major, &rev_minor,
			&rev_rc);
	xil_printf("rev_major = 0x%x, rev_minor = 0x%x, rev_rc = 0x%x\r\n",
			rev_major, rev_minor, rev_rc);
	if (API_CMS_ERROR_OK != err)
	{
		PRINT_RED
		xil_printf("adi_ad9082_device_api_revision_get ERR = %d", err);
		PRINT_NORM
	}
	err = adi_ad9082_device_reset(device, AD9082_HARD_RESET);
	if (API_CMS_ERROR_OK != err)
	{
		PRINT_RED
		xil_printf("adi_ad9082_device_reset ERR = %d", err);
		PRINT_NORM
	}
	err = adi_ad9082_device_init(device);
	if (API_CMS_ERROR_OK != err)
	{
		PRINT_RED
		xil_printf("adi_ad9082_device_init ERR = %d", err);
		PRINT_NORM
	}
	err = adi_ad9082_device_clk_config_set(device, dac_clk_hz, adc_clk_hz,
			ref_clk_hz);
	if (API_CMS_ERROR_OK != err)
	{
		PRINT_RED
		xil_printf("adi_ad9082_device_clk_config_set ERR = %d", err);
		PRINT_NORM
	}
//------------------------------------------------------------------------------------

The output of the above function calls is as below:

VCU118_CODE
INFO: GPIO_INIT_DEV 0 OK
INFO: GPIO_INIT_DEV 1 OK
txCmd = 0x0000, Data 0x18

 ------ SET ADC MODE TO 4 WIRE MODE ------

ADC_SET_4_WIRE_PASS

------- init_hmc --------

==================================

init_adc_api_Structure
init_jesd_param
INIT_DONE
=====================================
============ ADC_INFO ===============
=====================================

{API} adi_ad9082_device_chip_id_get(...)
txCmd = 0x0000, Data 0x18

 ------ SET ADC MODE TO 4 WIRE MODE ------

ADC_SET_4_WIRE_PASS

{SPI} ad9082: r@0003 = 0f

{SPI} ad9082: r@0004 = 82

{SPI} ad9082: r@0005 = 90

{SPI} ad9082: r@0006 = 23
 chip_type     = 0xF
 dev_revision  = 0x3
 prod_grade    = 0x2
 prod_id       = 0x9082
=====================================

{API} adi_ad9082_device_api_revision_get(...)
rev_major = 0x1, rev_minor = 0x2, rev_rc = 0x2

{API} adi_ad9082_device_reset(...)

{API} adi_ad9082_device_init(...)
txCmd = 0x0000, Data 0x18

 ------ SET ADC MODE TO 4 WIRE MODE ------

ADC_SET_4_WIRE_PASS

{LOG} api v1.2.2 commit 5b813df for ad9082

{LOG} host is using little endian mode.

{API} adi_ad9082_device_spi_config(...)
txCmd = 0x0000, Data 0x18

 ------ SET ADC MODE TO 4 WIRE MODE ------

{SPI} ad9082: w@0000 = 18

{API} adi_ad9082_device_reg8_access_check(...)

{SPI} ad9082: r@001c = ff

{SPI} ad9082: w@001c = 5a

{SPI} ad9082: r@001c = 5a

{SPI} ad9082: w@001c = a5

{SPI} ad9082: r@001c = a5

{SPI} ad9082: w@001c = ff

{API} adi_ad9082_device_power_status_check(...)

{SPI} ad9082: r@0210 = 3f

{SPI} ad9082: r@0211 = 0f

{SPI} ad9082: r@0212 = 3f

{SPI} ad9082: r@0213 = 3f

{API} adi_ad9082_device_clk_config_set(...)

{API} adi_ad9082_device_boot_pre_clock(...)

{SPI} ad9082: r@3742 = 71

{API} adi_ad9082_device_chip_id_get(...)

{SPI} ad9082: r@0003 = 00

{SPI} ad9082: r@0004 = 00

{SPI} ad9082: r@0005 = 00

{SPI} ad9082: r@0006 = 00

{LOG} device is ad0 r0

{ERROR} Current device revision is not supported
adi_ad9082_device_clk_config_set ERR = -1
*
=====================================
============ ADC_INFO ===============
=====================================

{API} adi_ad9082_device_chip_id_get(...)

{SPI} ad9082: r@0003 = 00

{SPI} ad9082: r@0004 = 00

{SPI} ad9082: r@0005 = 00

{SPI} ad9082: r@0006 = 00
 chip_type     = 0x0
 dev_revision  = 0x0
 prod_grade    = 0x0
 prod_id       = 0x0
=====================================

*

The SPI bus fails to read after execution of code.

The following few observations are made with respect to UG1578 & API CALLS.
a) After reading in core status reg 0x3742 in adi_ad9082_device_boot_pre_clock function, SPI bus stops working, data read is 0x71. Details of the REG 0x3742 is no where provided in the UG1578. Other registers 0x3740 to 0x3743 & 0x21b2 used in function adi_ad9082_device_boot_pre_clock are also not available in UG1578.

b) In UG1578, Table 11 discusses about LCPLL Registers and Settings, the details are not provided for these registers in Table 195.

c) In UG1578, Table 61, last column, Reg 0x00CA values to be populated are shown, but the details of reg 0x00CA are not provided in Table 195.

similar other observations are made where UG1578 / API CALLS discusses about registers that are not described in Table 195, creating gaps in understanding of configuration values and order.

I have attached the basic requirement of my project, the ADC data is to be directly fed directly to bypass mode, the path to be set is highlighted in RED.

ADC PATH

It is requested to provide list and order of registers to be set to achieve the highlighted path, also provide API calls and argument values to meet this requirement.

Regards,
Faiz Ahmed.

PS: I had run the code and listed the address preset in API but not in UG1578. It is observed that when ever these address are executed, the SPI bus stops to work for all further calls.

0x3742
0x21B2
0x21B2
0x21B3
0x21B3
0x21B3
0x21B3
0x21B4
0x21B4
0x21B4
0x21B4
0x21B5
0x21B3
0x21B3
0x3743
0x3740



Added list of registers which are not available in UG1578.
[edited by: faiz321 at 6:46 AM (GMT -4) on 6 Jun 2022]
  • Hi, what is the sample rate used? What JTx mode are you using? for starters, can you try one of the canned use cases in the ucsettings file? you can try this as a starter
    { 125e6,    375e6,    8000e6,     4000e6    }, /* uc22, 204C,   100MHz,             24.75000Gbps, rx only   */

    also, are you using the onchip pll for the ad9082?

  • We have integrated the API and ran the use case 22.
    It was observed that post accessing of few registers (the registers which are not available in UG1578) the ADC does not respond onto the SPI bus.
    for example :
    At line 197 of LOG_A.txt

    VCU118_CODE
    INFO: GPIO_INIT_DEV 0 OK
    INFO: GPIO_INIT_DEV 1 OK
    0x0000 = 0x0
    txCmd = 0x0000, Data 0x18
    
     ------ SET ADC MODE TO 4 WIRE MODE ------
    
    ADC_SET_4_WIRE_PASS
    INIT_DONE
    Running uc22 on CE board using hmc7044.
    init_adc_api_Structure
    init_jesd_param
    On board crystal select: MHz
    
    {API} adi_ad9082_device_api_revision_get(...)
    AD9082 API v1.2.2
    FPGA Image MY OWN
    APP: Configure Usecase:22, Tx Path: DAC Clk: -589934592, JESD Rx Mode: 1 & Rx Path: ADC CLK: 0, Jesdmode Tx Mode: -294967296
    {API} adi_ad9082_device_reset(...)
    APP: Configure Platform Reference Clocks
    @set_hmc_spi 0x9F 0x4D
    @set_hmc_spi 0xA0 0xDF
    @set_hmc_spi 0xA5 0x6
    @set_hmc_spi 0xA8 0x6
    @set_hmc_spi 0xB0 0x4
    @set_hmc_spi 0x0 0x1
    @set_hmc_spi 0x0 0x0
    @set_hmc_spi 0x9F 0x4D
    @set_hmc_spi 0xA0 0xDF
    @set_hmc_spi 0xA5 0x6
    @set_hmc_spi 0xA8 0x6
    @set_hmc_spi 0xB0 0x4
    @set_hmc_spi 0xC8 0xF2
    @set_hmc_spi 0xD2 0xFC
    @set_hmc_spi 0xDC 0xF2
    @set_hmc_spi 0xE6 0xFC
    @set_hmc_spi 0xF0 0xF2
    @set_hmc_spi 0xFA 0xFC
    @set_hmc_spi 0x104 0xF2
    @set_hmc_spi 0x10E 0xFC
    @set_hmc_spi 0x118 0xF2
    @set_hmc_spi 0x122 0xFC
    @set_hmc_spi 0x12C 0xF2
    @set_hmc_spi 0x136 0xFC
    @set_hmc_spi 0x140 0xF2
    @set_hmc_spi 0x14A 0xFC
    @set_hmc_spi 0xA 0x7
    @set_hmc_spi 0xB 0x7
    @set_hmc_spi 0x15 0x7
    @set_hmc_spi 0x19 0x0
    @set_hmc_spi 0x3 0x2F
    @set_hmc_spi 0xE6 0xF0
    @set_hmc_spi 0x14A 0xF0
    @set_hmc_spi 0x14A 0xF0
    @set_hmc_spi 0x1 0x42
    @set_hmc_spi 0x1 0x40
    @set_hmc_spi 0xA 0x7
    @set_hmc_spi 0xB 0x7
    @set_hmc_spi 0xC 0x7
    @set_hmc_spi 0xD 0x7
    @set_hmc_spi 0xE 0x7
    @set_hmc_spi 0x14 0xE1
    @set_hmc_spi 0x1C 0x1
    @set_hmc_spi 0x1D 0x1
    @set_hmc_spi 0x1E 0x1
    @set_hmc_spi 0x1F 0x1
    @set_hmc_spi 0x20 0x1
    @set_hmc_spi 0x21 0x2
    @set_hmc_spi 0x22 0x0
    @set_hmc_spi 0x26 0x2
    @set_hmc_spi 0x27 0x0
    @set_hmc_spi 0x33 0x1
    @set_hmc_spi 0x34 0x0
    @set_hmc_spi 0x35 0xF
    @set_hmc_spi 0x36 0x0
    @set_hmc_spi 0x32 0x0
    @set_hmc_spi 0x1 0x42
    @set_hmc_spi 0x1 0x40
    @set_hmc_spi 0x9F 0x4D
    @set_hmc_spi 0xA0 0xDF
    @set_hmc_spi 0xA5 0x6
    @set_hmc_spi 0xA8 0x6
    @set_hmc_spi 0xB0 0x4
    @set_hmc_spi 0xD0 0x3
    @set_hmc_spi 0xC8 0x73
    @set_hmc_spi 0xC9 0x8
    @set_hmc_spi 0xCA 0x0
    @set_hmc_spi 0xCF 0x0
    @set_hmc_spi 0xE4 0x3
    @set_hmc_spi 0xDC 0x73
    @set_hmc_spi 0xDD 0x18
    @set_hmc_spi 0xDE 0x0
    @set_hmc_spi 0xE3 0x0
    @set_hmc_spi 0xEE 0x3
    @set_hmc_spi 0xE6 0x71
    @set_hmc_spi 0xE7 0x0
    @set_hmc_spi 0xE8 0x1
    @set_hmc_spi 0xED 0x0
    @set_hmc_spi 0x10C 0x3
    @set_hmc_spi 0x104 0x73
    @set_hmc_spi 0x105 0x8
    @set_hmc_spi 0x106 0x0
    @set_hmc_spi 0x10B 0x0
    @set_hmc_spi 0x120 0x3
    @set_hmc_spi 0x118 0x73
    @set_hmc_spi 0x119 0x8
    @set_hmc_spi 0x11A 0x0
    @set_hmc_spi 0x11F 0x0
    @set_hmc_spi 0x134 0x3
    @set_hmc_spi 0x12C 0x73
    @set_hmc_spi 0x12D 0x8
    @set_hmc_spi 0x12E 0x0
    @set_hmc_spi 0x133 0x0
    @set_hmc_spi 0x148 0x3
    @set_hmc_spi 0x140 0x73
    @set_hmc_spi 0x141 0x8
    @set_hmc_spi 0x142 0x0
    @set_hmc_spi 0x147 0x0
    @set_hmc_spi 0x152 0x3
    @set_hmc_spi 0x14A 0x71
    @set_hmc_spi 0x14B 0x0
    @set_hmc_spi 0x14C 0x1
    @set_hmc_spi 0x151 0x0
    @set_hmc_spi 0x1 0x42
    @set_hmc_spi 0x1 0x40
    APP: Reference Clocks Configured
    APP: Configure FPGA JESD Interfaces
    APP: FPGA JESD Interfaces Configured
    APP: Configure ad9082 Device
    
    {API} adi_ad9082_device_reset(...)
    0x0000 = 0x0
    txCmd = 0x0000, Data 0x18
    
     ------ SET ADC MODE TO 4 WIRE MODE ------
    
    ADC_SET_4_WIRE_PASS
    txCmd = 0x0000, Data 0x81
    >>>>Forced ADC to 4 wire
    0x0000 = 0x18
    
    ADC_SET_4_WIRE_PASS
    
    {SPI} ad9082: w@0000 = 81
    txCmd = 0x0000, Data 0x0
    >>>>Forced ADC to 4 wire
    0x0000 = 0x18
    
    ADC_SET_4_WIRE_PASS
    
    {SPI} ad9082: w@0000 = 00
    
    {API} adi_ad9082_device_init(...)
    
    {LOG} api v1.2.2 commit 5b813df for ad9082
    
    {LOG} host is using little endian mode.
    
    {API} adi_ad9082_device_spi_config(...)
    txCmd = 0x0000, Data 0x3C
    >>>>Forced ADC to 4 wire
    0x0000 = 0x18
    
    ADC_SET_4_WIRE_PASS
    
    {SPI} ad9082: w@0000 = 3c
    
    {API} adi_ad9082_device_reg8_access_check(...)
    
    {SPI} ad9082: r@001c = 5a
    
    {SPI} ad9082: w@001c = 5a
    
    {SPI} ad9082: r@001c = 5a
    
    {SPI} ad9082: w@001c = a5
    
    {SPI} ad9082: r@001c = a5
    
    {SPI} ad9082: w@001c = 5a
    
    {API} adi_ad9082_device_power_status_check(...)
    
    {SPI} ad9082: r@0210 = 3f
    
    {SPI} ad9082: r@0211 = 0f
    
    {SPI} ad9082: r@0212 = 3f
    
    {SPI} ad9082: r@0213 = 3f
    
    {API} adi_ad9082_device_clk_config_set(...)
    
    {API} adi_ad9082_device_boot_pre_clock(...)
    
    {SPI} ad9082: r@3742 = 71
    
    {API} adi_ad9082_device_chip_id_get(...)
    
    {SPI} ad9082: r@0003 = 00
    
    {SPI} ad9082: r@0004 = 00
    
    {SPI} ad9082: r@0005 = 00
    
    {SPI} ad9082: r@0006 = 00
    
    {LOG} device is ad0 r0
    
    {ERROR} Current device revision is not supported
    
    {API} adi_ad9082_device_clk_pll_lock_status_get(...)
    
    {SPI} ad9082: r@2008 = 00
    APP: Clock Configration error
    
    *
    
    

    when register 0x3742 was tried to read, value 0x71 was read successfully, but after that access of register 0x3742, SPI access to all registers after that command failed.
    The log of the run is attached as LOG_A.txt.

    To overcome the above observation, when ever API tried to access the SPI registers which were not listed in UG1578, the read or write calls were bypassed.
    The log of the run is attached as LOG_B.txt.

    VCU118_CODE
    INFO: GPIO_INIT_DEV 0 OK
    INFO: GPIO_INIT_DEV 1 OK
    0x0000 = 0x0
    
     ------ SET ADC MODE TO 4 WIRE MODE ------
    
    ADC_SET_4_WIRE_PASS
    INIT_DONE
    Running uc22 on CE board using hmc7044.
    init_adc_api_Structure
    init_jesd_param
    On board crystal select: MHz
    
    {API} adi_ad9082_device_api_revision_get(...)
    AD9082 API v1.2.2
    FPGA Image MY OWN
    APP: Configure Usecase:22, Tx Path: DAC Clk: -589934592, JESD Rx Mode: 1 & Rx Path: ADC CLK: 0, Jesdmode Tx Mode: -294967296
    {API} adi_ad9082_device_reset(...)
    APP: Configure Platform Reference Clocks
    @set_hmc_spi 0x9F 0x4D
    @set_hmc_spi 0xA0 0xDF
    @set_hmc_spi 0xA5 0x6
    @set_hmc_spi 0xA8 0x6
    @set_hmc_spi 0xB0 0x4
    @set_hmc_spi 0x0 0x1
    @set_hmc_spi 0x0 0x0
    @set_hmc_spi 0x9F 0x4D
    @set_hmc_spi 0xA0 0xDF
    @set_hmc_spi 0xA5 0x6
    @set_hmc_spi 0xA8 0x6
    @set_hmc_spi 0xB0 0x4
    @set_hmc_spi 0xC8 0xF2
    @set_hmc_spi 0xD2 0xFC
    @set_hmc_spi 0xDC 0xF2
    @set_hmc_spi 0xE6 0xFC
    @set_hmc_spi 0xF0 0xF2
    @set_hmc_spi 0xFA 0xFC
    @set_hmc_spi 0x104 0xF2
    @set_hmc_spi 0x10E 0xFC
    @set_hmc_spi 0x118 0xF2
    @set_hmc_spi 0x122 0xFC
    @set_hmc_spi 0x12C 0xF2
    @set_hmc_spi 0x136 0xFC
    @set_hmc_spi 0x140 0xF2
    @set_hmc_spi 0x14A 0xFC
    @set_hmc_spi 0xA 0x7
    @set_hmc_spi 0xB 0x7
    @set_hmc_spi 0x15 0x7
    @set_hmc_spi 0x19 0x0
    @set_hmc_spi 0x3 0x2F
    @set_hmc_spi 0xE6 0xF0
    @set_hmc_spi 0x14A 0xF0
    @set_hmc_spi 0x14A 0xF0
    @set_hmc_spi 0x1 0x42
    @set_hmc_spi 0x1 0x40
    @set_hmc_spi 0xA 0x7
    @set_hmc_spi 0xB 0x7
    @set_hmc_spi 0xC 0x7
    @set_hmc_spi 0xD 0x7
    @set_hmc_spi 0xE 0x7
    @set_hmc_spi 0x14 0xE1
    @set_hmc_spi 0x1C 0x1
    @set_hmc_spi 0x1D 0x1
    @set_hmc_spi 0x1E 0x1
    @set_hmc_spi 0x1F 0x1
    @set_hmc_spi 0x20 0x1
    @set_hmc_spi 0x21 0x2
    @set_hmc_spi 0x22 0x0
    @set_hmc_spi 0x26 0x2
    @set_hmc_spi 0x27 0x0
    @set_hmc_spi 0x33 0x1
    @set_hmc_spi 0x34 0x0
    @set_hmc_spi 0x35 0xF
    @set_hmc_spi 0x36 0x0
    @set_hmc_spi 0x32 0x0
    @set_hmc_spi 0x1 0x42
    @set_hmc_spi 0x1 0x40
    @set_hmc_spi 0x9F 0x4D
    @set_hmc_spi 0xA0 0xDF
    @set_hmc_spi 0xA5 0x6
    @set_hmc_spi 0xA8 0x6
    @set_hmc_spi 0xB0 0x4
    @set_hmc_spi 0xD0 0x3
    @set_hmc_spi 0xC8 0x73
    @set_hmc_spi 0xC9 0x8
    @set_hmc_spi 0xCA 0x0
    @set_hmc_spi 0xCF 0x0
    @set_hmc_spi 0xE4 0x3
    @set_hmc_spi 0xDC 0x73
    @set_hmc_spi 0xDD 0x18
    @set_hmc_spi 0xDE 0x0
    @set_hmc_spi 0xE3 0x0
    @set_hmc_spi 0xEE 0x3
    @set_hmc_spi 0xE6 0x71
    @set_hmc_spi 0xE7 0x0
    @set_hmc_spi 0xE8 0x1
    @set_hmc_spi 0xED 0x0
    @set_hmc_spi 0x10C 0x3
    @set_hmc_spi 0x104 0x73
    @set_hmc_spi 0x105 0x8
    @set_hmc_spi 0x106 0x0
    @set_hmc_spi 0x10B 0x0
    @set_hmc_spi 0x120 0x3
    @set_hmc_spi 0x118 0x73
    @set_hmc_spi 0x119 0x8
    @set_hmc_spi 0x11A 0x0
    @set_hmc_spi 0x11F 0x0
    @set_hmc_spi 0x134 0x3
    @set_hmc_spi 0x12C 0x73
    @set_hmc_spi 0x12D 0x8
    @set_hmc_spi 0x12E 0x0
    @set_hmc_spi 0x133 0x0
    @set_hmc_spi 0x148 0x3
    @set_hmc_spi 0x140 0x73
    @set_hmc_spi 0x141 0x8
    @set_hmc_spi 0x142 0x0
    @set_hmc_spi 0x147 0x0
    @set_hmc_spi 0x152 0x3
    @set_hmc_spi 0x14A 0x71
    @set_hmc_spi 0x14B 0x0
    @set_hmc_spi 0x14C 0x1
    @set_hmc_spi 0x151 0x0
    @set_hmc_spi 0x1 0x42
    @set_hmc_spi 0x1 0x40
    APP: Reference Clocks Configured
    APP: Configure FPGA JESD Interfaces
    APP: FPGA JESD Interfaces Configured
    APP: Configure ad9082 Device
    
    {API} adi_ad9082_device_reset(...)
    0x0000 = 0x0
    
     ------ SET ADC MODE TO 4 WIRE MODE ------
    
    ADC_SET_4_WIRE_PASS
    
     !!!!!!! FAILED TO SET ADC MODE TO 4 WIRE MODE !!!!!!!
    
    {SPI} ad9082: w@0000 = 81
    
     !!!!!!! FAILED TO SET ADC MODE TO 4 WIRE MODE !!!!!!!
    
    {SPI} ad9082: w@0000 = 00
    
    {API} adi_ad9082_device_init(...)
    
    {LOG} api v1.2.2 commit 5b813df for ad9082
    
    {LOG} host is using little endian mode.
    
    {API} adi_ad9082_device_spi_config(...)
    
     ------ SET ADC MODE TO 4 WIRE MODE ------
    
    {SPI} ad9082: w@0000 = 3c
    
    {API} adi_ad9082_device_reg8_access_check(...)
    
    {SPI} ad9082: r@001c = ff
    
    {SPI} ad9082: w@001c = 5a
    
    {SPI} ad9082: r@001c = 5a
    
    {SPI} ad9082: w@001c = a5
    
    {SPI} ad9082: r@001c = a5
    
    {SPI} ad9082: w@001c = ff
    
    {API} adi_ad9082_device_power_status_check(...)
    
    {SPI} ad9082: r@0210 = 3f
    
    {SPI} ad9082: r@0211 = 0f
    
    {SPI} ad9082: r@0212 = 3f
    
    {SPI} ad9082: r@0213 = 3f
    
    {API} adi_ad9082_device_clk_config_set(...)
    
    {API} adi_ad9082_device_boot_pre_clock(...)
    get input Reg 0x3742 not available in UG1578, sending pseudo value
    
    {SPI} ad9082: r@3742 = f1
    
    {API} adi_ad9082_device_chip_id_get(...)
    
    {SPI} ad9082: r@0003 = 0f
    
    {SPI} ad9082: r@0004 = 82
    
    {SPI} ad9082: r@0005 = 90
    
    {SPI} ad9082: r@0006 = 23
    
    {LOG} device is ad9082 r3
    
    {API} adi_ad9082_device_laminate_id_get(...)
    get input Reg 0x1E0D not available in UG1578, sending pseudo value
    
    {SPI} ad9082: r@1e0d = 03
    
    {API} adi_ad9082_device_die_id_get(...)
    get input Reg 0x1E0E not available in UG1578, sending pseudo value
    
    {SPI} ad9082: r@1e0e = 06
    get input Reg 0x21B2 not available in UG1578, sending pseudo value
    
    {SPI} ad9082: r@21b2 = 00
    set input Reg 0x21B2, setValue 0x10 not available in UG1578, skipping it
    
    {SPI} ad9082: w@21b2 = 10
    
    {API} adi_ad9082_device_digital_logic_enable_set(...)
    
    {SPI} ad9082: r@0201 = 01
    
    {SPI} ad9082: w@0201 = 00
    
    {SPI} ad9082: w@00d0 = 1f
    
    {API} adi_ad9082_device_aclk_receiver_enable_set(...)
    
    {SPI} ad9082: r@0091 = 00
    
    {SPI} ad9082: w@0091 = 00
    
    {API} adi_ad9082_device_clk_pll_enable_set(...)
    
    {SPI} ad9082: r@0094 = 00
    
    {SPI} ad9082: w@0094 = 01
    
    {SPI} ad9082: w@00e0 = 9f
    
    {SPI} ad9082: w@00e1 = 1f
    
    {API} adi_ad9082_device_clk_pll_startup(...)
    
    {API} adi_ad9082_device_clk_pll_enable_set(...)
    
    {SPI} ad9082: r@0094 = 01
    
    {SPI} ad9082: w@0094 = 00
    
    {SPI} ad9082: w@00e0 = 00
    
    {SPI} ad9082: w@00e1 = 00
    
    {API} adi_ad9082_device_clk_pll_div_set(...)
    
    {SPI} ad9082: w@00fe = fc
    
    {SPI} ad9082: r@00ff = 05
    
    {SPI} ad9082: w@00ff = 03
    
    {SPI} ad9082: w@00fa = ce
    
    {SPI} ad9082: r@00fb = 02
    
    {SPI} ad9082: w@00fb = 02
    
    {SPI} ad9082: r@00e8 = 00
    
    {SPI} ad9082: w@00e8 = 1f
    
    {SPI} ad9082: r@00e7 = 80
    
    {SPI} ad9082: w@00e7 = a0
    
    {SPI} ad9082: r@00e4 = 10
    
    {SPI} ad9082: w@00e4 = 13
    
    {SPI} ad9082: r@00e6 = d0
    
    {SPI} ad9082: w@00e6 = c0
    
    {SPI} ad9082: r@00e3 = 10
    
    {SPI} ad9082: w@00e3 = 08
    
    {SPI} ad9082: w@00e2 = 1f
    
    {SPI} ad9082: w@00e2 = 00
    
    {SPI} ad9082: r@00e3 = 08
    
    {SPI} ad9082: w@00e3 = 08
    
    {SPI} ad9082: r@0093 = 00
    
    {SPI} ad9082: w@0093 = 00
    
    {SPI} ad9082: r@00e9 = 08
    
    {SPI} ad9082: w@00e9 = 08
    
    {SPI} ad9082: r@00ec = 26
    
    {SPI} ad9082: w@00ec = 26
    
    {SPI} ad9082: r@00ee = 94
    
    {SPI} ad9082: w@00ee = 94
    
    {SPI} ad9082: w@00ea = 60
    
    {SPI} ad9082: w@00eb = 3d
    
    {SPI} ad9082: r@00e2 = 00
    
    {SPI} ad9082: w@00e2 = 02
    
    {SPI} ad9082: r@00e2 = 02
    
    {SPI} ad9082: w@00e2 = 00
    
    {API} adi_ad9082_device_clk_pll_lock_status_get(...)
    
    {SPI} ad9082: r@2008 = 02
    
    {API} adi_ad9082_device_clk_pll_lock_status_get(...)
    
    {SPI} ad9082: r@2008 = 03
    
    {API} adi_ad9082_adc_clk_div_set(...)
    
    {SPI} ad9082: r@0180 = 00
    
    {SPI} ad9082: w@0180 = 01
    
    {API} adi_ad9082_device_clk_up_div_set(...)
    
    {SPI} ad9082: r@00d0 = 00
    FAILED TO WRITE ADC DATA TO SPI REG 0xD0, WR->DATA 0x4, RD->DATA 0x0
    
    {SPI} ad9082: w@00d0 = 04
    get input Reg 0x21B3 not available in UG1578, sending pseudo value
    
    {SPI} ad9082: r@21b3 = 00
    set input Reg 0x21B3, setValue 0x2 not available in UG1578, skipping it
    
    {SPI} ad9082: w@21b3 = 02
    get input Reg 0x21B3 not available in UG1578, sending pseudo value
    
    {SPI} ad9082: r@21b3 = 00
    set input Reg 0x21B3, setValue 0x80 not available in UG1578, skipping it
    
    {SPI} ad9082: w@21b3 = 80
    get input Reg 0x21B4 not available in UG1578, sending pseudo value
    
    {SPI} ad9082: r@21b4 = 00
    set input Reg 0x21B4, setValue 0x2 not available in UG1578, skipping it
    
    {SPI} ad9082: w@21b4 = 02
    get input Reg 0x21B4 not available in UG1578, sending pseudo value
    
    {SPI} ad9082: r@21b4 = 00
    set input Reg 0x21B4, setValue 0x20 not available in UG1578, skipping it
    
    {SPI} ad9082: w@21b4 = 20
    set input Reg 0x21B5, setValue 0xA not available in UG1578, skipping it
    
    {SPI} ad9082: w@21b5 = 0a
    get input Reg 0x21B3 not available in UG1578, sending pseudo value
    
    {SPI} ad9082: r@21b3 = 00
    set input Reg 0x21B3, setValue 0x40 not available in UG1578, skipping it
    
    {SPI} ad9082: w@21b3 = 40
    
    {API} adi_ad9082_device_boot_post_clock(...)
    set input Reg 0x3743, setValue 0x1 not available in UG1578, skipping it
    
    {SPI} ad9082: w@3743 = 01
    get input Reg 0x3D26 not available in UG1578, sending pseudo value
    
    {SPI} ad9082: r@3d26 = 00
    set input Reg 0x3D26, setValue 0x8 not available in UG1578, skipping it
    
    {SPI} ad9082: w@3d26 = 08
    get input Reg 0x3D26 not available in UG1578, sending pseudo value
    
    {SPI} ad9082: r@3d26 = 00
    get input Reg 0x3740 not available in UG1578, sending pseudo value
    
    {SPI} ad9082: r@3740 = 01
    get input Reg 0x3742 not available in UG1578, sending pseudo value
    
    {SPI} ad9082: r@3742 = f1
    get input Reg 0x3740 not available in UG1578, sending pseudo value
    
    {SPI} ad9082: r@3740 = 01
    
    {ERROR} Clock switch not done
    
    {SPI} ad9082: w@2112 = 01
    
    {SPI} ad9082: r@00d1 = 00
    FAILED TO WRITE ADC DATA TO SPI REG 0xD1, WR->DATA 0x1, RD->DATA 0x0
    
    {SPI} ad9082: w@00d1 = 01
    
    {SPI} ad9082: r@00d1 = 00
    FAILED TO WRITE ADC DATA TO SPI REG 0xD1, WR->DATA 0x10, RD->DATA 0x0
    
    {SPI} ad9082: w@00d1 = 10
    
    {SPI} ad9082: r@00d1 = 00
    FAILED TO WRITE ADC DATA TO SPI REG 0xD1, WR->DATA 0x2, RD->DATA 0x0
    
    {SPI} ad9082: w@00d1 = 02
    
    {SPI} ad9082: r@00d1 = 00
    FAILED TO WRITE ADC DATA TO SPI REG 0xD1, WR->DATA 0x20, RD->DATA 0x0
    
    {SPI} ad9082: w@00d1 = 20
    set input Reg 0x1400, setValue 0xD4 not available in UG1578, skipping it
    
    {SPI} ad9082: w@1400 = d4
    
    {SPI} ad9082: r@00d1 = 00
    
    {SPI} ad9082: w@00d1 = 00
    
    {SPI} ad9082: r@00d1 = 00
    
    {SPI} ad9082: w@00d1 = 00
    
    {SPI} ad9082: r@00d1 = 00
    
    {SPI} ad9082: w@00d1 = 00
    
    {SPI} ad9082: r@00d1 = 00
    
    {SPI} ad9082: w@00d1 = 00
    
    {SPI} ad9082: w@2112 = 00
    FAILED TO WRITE ADC DATA TO SPI REG 0xD0, WR->DATA 0x1F, RD->DATA 0x0
    
    {SPI} ad9082: w@00d0 = 1f
    
    {API} adi_ad9082_adc_clk_enable_set(...)
    
    {SPI} ad9082: r@0180 = 01
    
    {SPI} ad9082: w@0180 = 01
    
    {API} adi_ad9082_device_clk_pll_lock_status_get(...)
    
    {SPI} ad9082: r@2008 = 03
    APP: ad9082 PLL LOCKED
    
    {API} adi_ad9082_adc_clk_out_enable_set(...)
    
    {SPI} ad9082: r@0198 = 00
    
    {SPI} ad9082: w@0198 = 00
    
    {API} adi_ad9082_adc_clk_out_voltage_swing_set(...)
    
    {SPI} ad9082: r@0196 = 00
    
    {SPI} ad9082: w@0196 = 00
    
    {API} adi_ad9082_device_startup_rx(...)
    
    {API} adi_ad9082_adc_config(...)
    
    {API} adi_ad9082_device_die_id_get(...)
    get input Reg 0x1E0E not available in UG1578, sending pseudo value
    
    {SPI} ad9082: r@1e0e = 06
    
    {SPI} ad9082: r@212c = 00
    
    {SPI} ad9082: w@212c = 00
    
    {SPI} ad9082: r@2114 = 00
    
    {SPI} ad9082: w@2114 = 20
    
    {SPI} ad9082: w@2100 = 01
    
    {API} adi_ad9082_adc_xbar_set(...)
    
    {API} adi_ad9082_adc_adc2cddc_xbar_set(...)
    
    {SPI} ad9082: r@0280 = 00
    FAILED TO WRITE ADC DATA TO SPI REG 0x280, WR->DATA 0x2, RD->DATA 0x0
    
    {SPI} ad9082: w@0280 = 02
    
    {API} adi_ad9082_adc_cddc2fddc_xbar_set(...)
    FAILED TO WRITE ADC DATA TO SPI REG 0x281, WR->DATA 0xAA, RD->DATA 0x0
    
    {SPI} ad9082: w@0281 = aa
    
    {API} adi_ad9082_adc_pfir_din_select_set(...)
    
    {API} adi_ad9082_adc_pfir_ctl_page_set(...)
    FAILED TO WRITE ADC DATA TO SPI REG 0x1E, WR->DATA 0x1, RD->DATA 0x0
    
    {SPI} ad9082: w@001e = 01
    
    {SPI} ad9082: r@0b12 = 00
    FAILED TO WRITE ADC DATA TO SPI REG 0xB12, WR->DATA 0x4, RD->DATA 0x0
    
    {SPI} ad9082: w@0b12 = 04
    
    {API} adi_ad9082_adc_ddc_coarse_nco_enable_set(...)
    
    {SPI} ad9082: r@0285 = 00
    FAILED TO WRITE ADC DATA TO SPI REG 0x285, WR->DATA 0xF, RD->DATA 0x0
    
    {SPI} ad9082: w@0285 = 0f
    
    {API} adi_ad9082_adc_ddc_fine_nco_enable_set(...)
    
    {SPI} ad9082: w@0286 = 00
    
    {API} adi_ad9082_adc_ddc_coarse_dcm_set(...)
    
    {API} adi_ad9082_adc_ddc_coarse_select_set(...)
    
    {SPI} ad9082: r@0018 = 00
    FAILED TO WRITE ADC DATA TO SPI REG 0x18, WR->DATA 0x10, RD->DATA 0x0
    
    {SPI} ad9082: w@0018 = 10
    
    {SPI} ad9082: r@0282 = 00
    FAILED TO WRITE ADC DATA TO SPI REG 0x282, WR->DATA 0xC, RD->DATA 0x0
    
    {SPI} ad9082: w@0282 = 0c
    
    {API} adi_ad9082_adc_ddc_coarse_c2r_set(...)
    
    {API} adi_ad9082_adc_ddc_coarse_select_set(...)
    
    {SPI} ad9082: r@0018 = 00
    FAILED TO WRITE ADC DATA TO SPI REG 0x18, WR->DATA 0x10, RD->DATA 0x0
    
    {SPI} ad9082: w@0018 = 10
    
    {SPI} ad9082: r@0282 = 00
    
    {SPI} ad9082: w@0282 = 00
    
    {API} adi_ad9082_adc_ddc_coarse_gain_set(...)
    
    {API} adi_ad9082_adc_ddc_coarse_select_set(...)
    
    {SPI} ad9082: r@0018 = 00
    FAILED TO WRITE ADC DATA TO SPI REG 0x18, WR->DATA 0x10, RD->DATA 0x0
    
    {SPI} ad9082: w@0018 = 10
    
    {SPI} ad9082: r@0282 = 00
    
    {SPI} ad9082: w@0282 = 00
    
    {API} adi_ad9082_adc_ddc_coarse_nco_mode_set(...)
    
    {API} adi_ad9082_adc_ddc_coarse_select_set(...)
    
    {SPI} ad9082: r@0018 = 00
    FAILED TO WRITE ADC DATA TO SPI REG 0x18, WR->DATA 0x10, RD->DATA 0x0
    
    {SPI} ad9082: w@0018 = 10
    
    {SPI} ad9082: r@0282 = 00
    FAILED TO WRITE ADC DATA TO SPI REG 0x282, WR->DATA 0x40, RD->DATA 0x0
    
    {SPI} ad9082: w@0282 = 40
    
    {API} adi_ad9082_adc_ddc_coarse_nco_set(...)
    
    {API} adi_ad9082_hal_calc_rx_nco_ftw(...)
    
    {API} adi_ad9082_adc_ddc_coarse_nco_ftw_set(...)
    
    {API} adi_ad9082_adc_ddc_coarse_select_set(...)
    
    {SPI} ad9082: r@0018 = 00
    FAILED TO WRITE ADC DATA TO SPI REG 0x18, WR->DATA 0x10, RD->DATA 0x0
    
    {SPI} ad9082: w@0018 = 10
    
    {SPI} ad9082: w@0a05 = 00
    
    {SPI} ad9082: w@0a06 = 00
    
    {SPI} ad9082: w@0a07 = 00
    
    {SPI} ad9082: w@0a08 = 00
    
    {SPI} ad9082: w@0a09 = 00
    
    {SPI} ad9082: w@0a0a = 00
    
    {SPI} ad9082: w@0a11 = 00
    
    {SPI} ad9082: w@0a12 = 00
    
    {SPI} ad9082: w@0a13 = 00
    
    {SPI} ad9082: w@0a14 = 00
    
    {SPI} ad9082: w@0a15 = 00
    
    {SPI} ad9082: w@0a16 = 00
    
    {SPI} ad9082: w@0a17 = 00
    
    {SPI} ad9082: w@0a18 = 00
    
    {SPI} ad9082: w@0a19 = 00
    
    {SPI} ad9082: w@0a1a = 00
    
    {SPI} ad9082: w@0a1b = 00
    
    {SPI} ad9082: w@0a1c = 00
    
    {API} adi_ad9082_adc_ddc_coarse_nco_phase_offset_set(...)
    
    {API} adi_ad9082_adc_ddc_coarse_select_set(...)
    
    {SPI} ad9082: r@0018 = 00
    FAILED TO WRITE ADC DATA TO SPI REG 0x18, WR->DATA 0x10, RD->DATA 0x0
    
    {SPI} ad9082: w@0018 = 10
    
    {SPI} ad9082: w@0a0b = 00
    
    {SPI} ad9082: w@0a0c = 00
    
    {SPI} ad9082: w@0a0d = 00
    
    {SPI} ad9082: w@0a0e = 00
    
    {SPI} ad9082: w@0a0f = 00
    
    {SPI} ad9082: w@0a10 = 00
    
    {API} adi_ad9082_adc_ddc_coarse_dcm_set(...)
    
    {API} adi_ad9082_adc_ddc_coarse_select_set(...)
    
    {SPI} ad9082: r@0018 = 00
    FAILED TO WRITE ADC DATA TO SPI REG 0x18, WR->DATA 0x20, RD->DATA 0x0
    
    {SPI} ad9082: w@0018 = 20
    
    {SPI} ad9082: r@0282 = 00
    FAILED TO WRITE ADC DATA TO SPI REG 0x282, WR->DATA 0xC, RD->DATA 0x0
    
    {SPI} ad9082: w@0282 = 0c
    
    {API} adi_ad9082_adc_ddc_coarse_c2r_set(...)
    
    {API} adi_ad9082_adc_ddc_coarse_select_set(...)
    
    {SPI} ad9082: r@0018 = 00
    FAILED TO WRITE ADC DATA TO SPI REG 0x18, WR->DATA 0x20, RD->DATA 0x0
    
    {SPI} ad9082: w@0018 = 20
    
    {SPI} ad9082: r@0282 = 00
    
    {SPI} ad9082: w@0282 = 00
    
    {API} adi_ad9082_adc_ddc_coarse_gain_set(...)
    
    {API} adi_ad9082_adc_ddc_coarse_select_set(...)
    
    {SPI} ad9082: r@0018 = 00
    FAILED TO WRITE ADC DATA TO SPI REG 0x18, WR->DATA 0x20, RD->DATA 0x0
    
    {SPI} ad9082: w@0018 = 20
    
    {SPI} ad9082: r@0282 = 00
    
    {SPI} ad9082: w@0282 = 00
    
    {API} adi_ad9082_adc_ddc_coarse_nco_mode_set(...)
    
    {API} adi_ad9082_adc_ddc_coarse_select_set(...)
    
    {SPI} ad9082: r@0018 = 00
    FAILED TO WRITE ADC DATA TO SPI REG 0x18, WR->DATA 0x20, RD->DATA 0x0
    
    {SPI} ad9082: w@0018 = 20
    
    {SPI} ad9082: r@0282 = 00
    FAILED TO WRITE ADC DATA TO SPI REG 0x282, WR->DATA 0x40, RD->DATA 0x0
    
    {SPI} ad9082: w@0282 = 40
    
    {API} adi_ad9082_adc_ddc_coarse_nco_set(...)
    
    {API} adi_ad9082_hal_calc_rx_nco_ftw(...)
    
    {API} adi_ad9082_adc_ddc_coarse_nco_ftw_set(...)
    
    {API} adi_ad9082_adc_ddc_coarse_select_set(...)
    
    {SPI} ad9082: r@0018 = 00
    FAILED TO WRITE ADC DATA TO SPI REG 0x18, WR->DATA 0x20, RD->DATA 0x0
    
    {SPI} ad9082: w@0018 = 20
    
    {SPI} ad9082: w@0a05 = 00
    
    {SPI} ad9082: w@0a06 = 00
    
    {SPI} ad9082: w@0a07 = 00
    
    {SPI} ad9082: w@0a08 = 00
    
    {SPI} ad9082: w@0a09 = 00
    
    {SPI} ad9082: w@0a0a = 00
    
    {SPI} ad9082: w@0a11 = 00
    
    {SPI} ad9082: w@0a12 = 00
    
    {SPI} ad9082: w@0a13 = 00
    
    {SPI} ad9082: w@0a14 = 00
    
    {SPI} ad9082: w@0a15 = 00
    
    {SPI} ad9082: w@0a16 = 00
    
    {SPI} ad9082: w@0a17 = 00
    
    {SPI} ad9082: w@0a18 = 00
    
    {SPI} ad9082: w@0a19 = 00
    
    {SPI} ad9082: w@0a1a = 00
    
    {SPI} ad9082: w@0a1b = 00
    
    {SPI} ad9082: w@0a1c = 00
    
    {API} adi_ad9082_adc_ddc_coarse_nco_phase_offset_set(...)
    
    {API} adi_ad9082_adc_ddc_coarse_select_set(...)
    
    {SPI} ad9082: r@0018 = 00
    FAILED TO WRITE ADC DATA TO SPI REG 0x18, WR->DATA 0x20, RD->DATA 0x0
    
    {SPI} ad9082: w@0018 = 20
    
    {SPI} ad9082: w@0a0b = 00
    
    {SPI} ad9082: w@0a0c = 00
    
    {SPI} ad9082: w@0a0d = 00
    
    {SPI} ad9082: w@0a0e = 00
    
    {SPI} ad9082: w@0a0f = 00
    
    {SPI} ad9082: w@0a10 = 00
    
    {API} adi_ad9082_adc_ddc_coarse_dcm_set(...)
    
    {API} adi_ad9082_adc_ddc_coarse_select_set(...)
    
    {SPI} ad9082: r@0018 = 00
    FAILED TO WRITE ADC DATA TO SPI REG 0x18, WR->DATA 0x40, RD->DATA 0x0
    
    {SPI} ad9082: w@0018 = 40
    
    {SPI} ad9082: r@0282 = 00
    FAILED TO WRITE ADC DATA TO SPI REG 0x282, WR->DATA 0xC, RD->DATA 0x0
    
    {SPI} ad9082: w@0282 = 0c
    
    {API} adi_ad9082_adc_ddc_coarse_c2r_set(...)
    
    {API} adi_ad9082_adc_ddc_coarse_select_set(...)
    
    {SPI} ad9082: r@0018 = 00
    FAILED TO WRITE ADC DATA TO SPI REG 0x18, WR->DATA 0x40, RD->DATA 0x0
    
    {SPI} ad9082: w@0018 = 40
    
    {SPI} ad9082: r@0282 = 00
    
    {SPI} ad9082: w@0282 = 00
    
    {API} adi_ad9082_adc_ddc_coarse_gain_set(...)
    
    {API} adi_ad9082_adc_ddc_coarse_select_set(...)
    
    {SPI} ad9082: r@0018 = 00
    FAILED TO WRITE ADC DATA TO SPI REG 0x18, WR->DATA 0x40, RD->DATA 0x0
    
    {SPI} ad9082: w@0018 = 40
    
    {SPI} ad9082: r@0282 = 00
    
    {SPI} ad9082: w@0282 = 00
    
    {API} adi_ad9082_adc_ddc_coarse_nco_mode_set(...)
    
    {API} adi_ad9082_adc_ddc_coarse_select_set(...)
    
    {SPI} ad9082: r@0018 = 00
    FAILED TO WRITE ADC DATA TO SPI REG 0x18, WR->DATA 0x40, RD->DATA 0x0
    
    {SPI} ad9082: w@0018 = 40
    
    {SPI} ad9082: r@0282 = 00
    FAILED TO WRITE ADC DATA TO SPI REG 0x282, WR->DATA 0x40, RD->DATA 0x0
    
    {SPI} ad9082: w@0282 = 40
    
    {API} adi_ad9082_adc_ddc_coarse_nco_set(...)
    
    {API} adi_ad9082_hal_calc_rx_nco_ftw(...)
    
    {API} adi_ad9082_adc_ddc_coarse_nco_ftw_set(...)
    
    {API} adi_ad9082_adc_ddc_coarse_select_set(...)
    
    {SPI} ad9082: r@0018 = 00
    FAILED TO WRITE ADC DATA TO SPI REG 0x18, WR->DATA 0x40, RD->DATA 0x0
    
    {SPI} ad9082: w@0018 = 40
    
    {SPI} ad9082: w@0a05 = 00
    
    {SPI} ad9082: w@0a06 = 00
    
    {SPI} ad9082: w@0a07 = 00
    
    {SPI} ad9082: w@0a08 = 00
    
    {SPI} ad9082: w@0a09 = 00
    
    {SPI} ad9082: w@0a0a = 00
    
    {SPI} ad9082: w@0a11 = 00
    
    {SPI} ad9082: w@0a12 = 00
    
    {SPI} ad9082: w@0a13 = 00
    
    {SPI} ad9082: w@0a14 = 00
    
    {SPI} ad9082: w@0a15 = 00
    
    {SPI} ad9082: w@0a16 = 00
    
    {SPI} ad9082: w@0a17 = 00
    
    {SPI} ad9082: w@0a18 = 00
    
    {SPI} ad9082: w@0a19 = 00
    
    {SPI} ad9082: w@0a1a = 00
    
    {SPI} ad9082: w@0a1b = 00
    
    {SPI} ad9082: w@0a1c = 00
    
    {API} adi_ad9082_adc_ddc_coarse_dcm_set(...)
    
    {API} adi_ad9082_adc_ddc_coarse_select_set(...)
    
    {SPI} ad9082: r@0018 = 00
    FAILED TO WRITE ADC DATA TO SPI REG 0x18, WR->DATA 0x80, RD->DATA 0x0
    
    {SPI} ad9082: w@0018 = 80
    
    {SPI} ad9082: r@0282 = 00
    FAILED TO WRITE ADC DATA TO SPI REG 0x282, WR->DATA 0xC, RD->DATA 0x0
    
    {SPI} ad9082: w@0282 = 0c
    
    {API} adi_ad9082_adc_ddc_coarse_c2r_set(...)
    
    {API} adi_ad9082_adc_ddc_coarse_select_set(...)
    
    {SPI} ad9082: r@0018 = 00
    FAILED TO WRITE ADC DATA TO SPI REG 0x18, WR->DATA 0x80, RD->DATA 0x0
    
    {SPI} ad9082: w@0018 = 80
    
    {SPI} ad9082: r@0282 = 00
    
    {SPI} ad9082: w@0282 = 00
    
    {API} adi_ad9082_adc_ddc_coarse_gain_set(...)
    
    {API} adi_ad9082_adc_ddc_coarse_select_set(...)
    
    {SPI} ad9082: r@0018 = 00
    FAILED TO WRITE ADC DATA TO SPI REG 0x18, WR->DATA 0x80, RD->DATA 0x0
    
    {SPI} ad9082: w@0018 = 80
    
    {SPI} ad9082: r@0282 = 00
    
    {SPI} ad9082: w@0282 = 00
    
    {API} adi_ad9082_adc_ddc_coarse_nco_mode_set(...)
    
    {API} adi_ad9082_adc_ddc_coarse_select_set(...)
    
    {SPI} ad9082: r@0018 = 00
    FAILED TO WRITE ADC DATA TO SPI REG 0x18, WR->DATA 0x80, RD->DATA 0x0
    
    {SPI} ad9082: w@0018 = 80
    
    {SPI} ad9082: r@0282 = 00
    FAILED TO WRITE ADC DATA TO SPI REG 0x282, WR->DATA 0x40, RD->DATA 0x0
    
    {SPI} ad9082: w@0282 = 40
    
    {API} adi_ad9082_adc_ddc_coarse_nco_set(...)
    
    {API} adi_ad9082_hal_calc_rx_nco_ftw(...)
    
    {API} adi_ad9082_adc_ddc_coarse_nco_ftw_set(...)
    
    {API} adi_ad9082_adc_ddc_coarse_select_set(...)
    
    {SPI} ad9082: r@0018 = 00
    FAILED TO WRITE ADC DATA TO SPI REG 0x18, WR->DATA 0x80, RD->DATA 0x0
    
    {SPI} ad9082: w@0018 = 80
    
    {SPI} ad9082: w@0a05 = 00
    
    {SPI} ad9082: w@0a06 = 00
    
    {SPI} ad9082: w@0a07 = 00
    
    {SPI} ad9082: w@0a08 = 00
    
    {SPI} ad9082: w@0a09 = 00
    
    {SPI} ad9082: w@0a0a = 00
    
    {SPI} ad9082: w@0a11 = 00
    
    {SPI} ad9082: w@0a12 = 00
    
    {SPI} ad9082: w@0a13 = 00
    
    {SPI} ad9082: w@0a14 = 00
    
    {SPI} ad9082: w@0a15 = 00
    
    {SPI} ad9082: w@0a16 = 00
    
    {SPI} ad9082: w@0a17 = 00
    
    {SPI} ad9082: w@0a18 = 00
    
    {SPI} ad9082: w@0a19 = 00
    
    {SPI} ad9082: w@0a1a = 00
    
    {SPI} ad9082: w@0a1b = 00
    
    {SPI} ad9082: w@0a1c = 00
    
    {API} adi_ad9082_adc_ddc_fine_dcm_set(...)
    
    {API} adi_ad9082_adc_ddc_fine_select_set(...)
    FAILED TO WRITE ADC DATA TO SPI REG 0x19, WR->DATA 0x1, RD->DATA 0x0
    
    {SPI} ad9082: w@0019 = 01
    
    {SPI} ad9082: r@0287 = 00
    FAILED TO WRITE ADC DATA TO SPI REG 0x287, WR->DATA 0x1, RD->DATA 0x0
    
    {SPI} ad9082: w@0287 = 01
    
    {API} adi_ad9082_adc_ddc_fine_c2r_set(...)
    
    {API} adi_ad9082_adc_ddc_fine_select_set(...)
    FAILED TO WRITE ADC DATA TO SPI REG 0x19, WR->DATA 0x1, RD->DATA 0x0
    
    {SPI} ad9082: w@0019 = 01
    
    {SPI} ad9082: r@0283 = 00
    
    {SPI} ad9082: w@0283 = 00
    
    {API} adi_ad9082_adc_ddc_fine_gain_set(...)
    
    {API} adi_ad9082_adc_ddc_fine_select_set(...)
    FAILED TO WRITE ADC DATA TO SPI REG 0x19, WR->DATA 0x1, RD->DATA 0x0
    
    {SPI} ad9082: w@0019 = 01
    
    {SPI} ad9082: r@0283 = 00
    
    {SPI} ad9082: w@0283 = 00
    
    {API} adi_ad9082_adc_ddc_fine_nco_mode_set(...)
    
    {API} adi_ad9082_adc_ddc_fine_select_set(...)
    FAILED TO WRITE ADC DATA TO SPI REG 0x19, WR->DATA 0x1, RD->DATA 0x0
    
    {SPI} ad9082: w@0019 = 01
    
    {SPI} ad9082: r@0283 = 00
    FAILED TO WRITE ADC DATA TO SPI REG 0x283, WR->DATA 0x40, RD->DATA 0x0
    
    {SPI} ad9082: w@0283 = 40
    
    {API} adi_ad9082_hal_calc_tx_nco_ftw(...)
    
    {API} adi_ad9082_adc_ddc_fine_nco_ftw_set(...)
    
    {API} adi_ad9082_adc_ddc_fine_select_set(...)
    FAILED TO WRITE ADC DATA TO SPI REG 0x19, WR->DATA 0x1, RD->DATA 0x0
    
    {SPI} ad9082: w@0019 = 01
    
    {SPI} ad9082: w@0a85 = 00
    
    {SPI} ad9082: w@0a86 = 00
    
    {SPI} ad9082: w@0a87 = 00
    
    {SPI} ad9082: w@0a88 = 00
    
    {SPI} ad9082: w@0a89 = 00
    
    {SPI} ad9082: w@0a8a = 00
    
    {SPI} ad9082: w@0a91 = 00
    
    {SPI} ad9082: w@0a92 = 00
    
    {SPI} ad9082: w@0a93 = 00
    
    {SPI} ad9082: w@0a94 = 00
    
    {SPI} ad9082: w@0a95 = 00
    
    {SPI} ad9082: w@0a96 = 00
    
    {SPI} ad9082: w@0a97 = 00
    
    {SPI} ad9082: w@0a98 = 00
    
    {SPI} ad9082: w@0a99 = 00
    
    {SPI} ad9082: w@0a9a = 00
    
    {SPI} ad9082: w@0a9b = 00
    
    {SPI} ad9082: w@0a9c = 00
    
    {API} adi_ad9082_adc_ddc_fine_overall_dcm_set(...)
    
    {API} adi_ad9082_adc_ddc_fine_select_set(...)
    FAILED TO WRITE ADC DATA TO SPI REG 0x19, WR->DATA 0x1, RD->DATA 0x0
    
    {SPI} ad9082: w@0019 = 01
    FAILED TO WRITE ADC DATA TO SPI REG 0x284, WR->DATA 0x1, RD->DATA 0x0
    
    {SPI} ad9082: w@0284 = 01
    
    {API} adi_ad9082_adc_ddc_fine_dcm_set(...)
    
    {API} adi_ad9082_adc_ddc_fine_select_set(...)
    FAILED TO WRITE ADC DATA TO SPI REG 0x19, WR->DATA 0x2, RD->DATA 0x0
    
    {SPI} ad9082: w@0019 = 02
    
    {SPI} ad9082: r@0287 = 00
    FAILED TO WRITE ADC DATA TO SPI REG 0x287, WR->DATA 0x2, RD->DATA 0x0
    
    {SPI} ad9082: w@0287 = 02
    
    {API} adi_ad9082_adc_ddc_fine_c2r_set(...)
    
    {API} adi_ad9082_adc_ddc_fine_select_set(...)
    FAILED TO WRITE ADC DATA TO SPI REG 0x19, WR->DATA 0x2, RD->DATA 0x0
    
    {SPI} ad9082: w@0019 = 02
    
    {SPI} ad9082: r@0283 = 00
    
    {SPI} ad9082: w@0283 = 00
    
    {API} adi_ad9082_adc_ddc_fine_gain_set(...)
    
    {API} adi_ad9082_adc_ddc_fine_select_set(...)
    FAILED TO WRITE ADC DATA TO SPI REG 0x19, WR->DATA 0x2, RD->DATA 0x0
    
    {SPI} ad9082: w@0019 = 02
    
    {SPI} ad9082: r@0283 = 00
    
    {SPI} ad9082: w@0283 = 00
    
    {API} adi_ad9082_adc_ddc_fine_nco_mode_set(...)
    
    {API} adi_ad9082_adc_ddc_fine_select_set(...)
    FAILED TO WRITE ADC DATA TO SPI REG 0x19, WR->DATA 0x2, RD->DATA 0x0
    
    {SPI} ad9082: w@0019 = 02
    
    {SPI} ad9082: r@0283 = 00
    FAILED TO WRITE ADC DATA TO SPI REG 0x283, WR->DATA 0x40, RD->DATA 0x0
    
    {SPI} ad9082: w@0283 = 40
    
    {API} adi_ad9082_hal_calc_tx_nco_ftw(...)
    
    {API} adi_ad9082_adc_ddc_fine_nco_ftw_set(...)
    
    {API} adi_ad9082_adc_ddc_fine_select_set(...)
    FAILED TO WRITE ADC DATA TO SPI REG 0x19, WR->DATA 0x2, RD->DATA 0x0
    
    {SPI} ad9082: w@0019 = 02
    
    {SPI} ad9082: w@0a85 = 00
    
    {SPI} ad9082: w@0a86 = 00
    
    {SPI} ad9082: w@0a87 = 00
    
    {SPI} ad9082: w@0a88 = 00
    
    {SPI} ad9082: w@0a89 = 00
    
    {SPI} ad9082: w@0a8a = 00
    
    {SPI} ad9082: w@0a91 = 00
    
    {SPI} ad9082: w@0a92 = 00
    
    {SPI} ad9082: w@0a93 = 00
    
    {SPI} ad9082: w@0a94 = 00
    
    {SPI} ad9082: w@0a95 = 00
    
    {SPI} ad9082: w@0a96 = 00
    
    {SPI} ad9082: w@0a97 = 00
    
    {SPI} ad9082: w@0a98 = 00
    
    {SPI} ad9082: w@0a99 = 00
    
    {SPI} ad9082: w@0a9a = 00
    
    {SPI} ad9082: w@0a9b = 00
    
    {SPI} ad9082: w@0a9c = 00
    
    {API} adi_ad9082_adc_ddc_fine_overall_dcm_set(...)
    
    {API} adi_ad9082_adc_ddc_fine_select_set(...)
    FAILED TO WRITE ADC DATA TO SPI REG 0x19, WR->DATA 0x2, RD->DATA 0x0
    
    {SPI} ad9082: w@0019 = 02
    FAILED TO WRITE ADC DATA TO SPI REG 0x284, WR->DATA 0x1, RD->DATA 0x0
    
    {SPI} ad9082: w@0284 = 01
    
    {API} adi_ad9082_adc_ddc_fine_dcm_set(...)
    
    {API} adi_ad9082_adc_ddc_fine_select_set(...)
    FAILED TO WRITE ADC DATA TO SPI REG 0x19, WR->DATA 0x10, RD->DATA 0x0
    
    {SPI} ad9082: w@0019 = 10
    
    {SPI} ad9082: r@0287 = 00
    FAILED TO WRITE ADC DATA TO SPI REG 0x287, WR->DATA 0x10, RD->DATA 0x0
    
    {SPI} ad9082: w@0287 = 10
    
    {API} adi_ad9082_adc_ddc_fine_c2r_set(...)
    
    {API} adi_ad9082_adc_ddc_fine_select_set(...)
    FAILED TO WRITE ADC DATA TO SPI REG 0x19, WR->DATA 0x10, RD->DATA 0x0
    
    {SPI} ad9082: w@0019 = 10
    
    {SPI} ad9082: r@0283 = 00
    
    {SPI} ad9082: w@0283 = 00
    
    {API} adi_ad9082_adc_ddc_fine_gain_set(...)
    
    {API} adi_ad9082_adc_ddc_fine_select_set(...)
    FAILED TO WRITE ADC DATA TO SPI REG 0x19, WR->DATA 0x10, RD->DATA 0x0
    
    {SPI} ad9082: w@0019 = 10
    
    {SPI} ad9082: r@0283 = 00
    
    {SPI} ad9082: w@0283 = 00
    
    {API} adi_ad9082_adc_ddc_fine_nco_mode_set(...)
    
    {API} adi_ad9082_adc_ddc_fine_select_set(...)
    FAILED TO WRITE ADC DATA TO SPI REG 0x19, WR->DATA 0x10, RD->DATA 0x0
    
    {SPI} ad9082: w@0019 = 10
    
    {SPI} ad9082: r@0283 = 00
    FAILED TO WRITE ADC DATA TO SPI REG 0x283, WR->DATA 0x40, RD->DATA 0x0
    
    {SPI} ad9082: w@0283 = 40
    
    {API} adi_ad9082_hal_calc_tx_nco_ftw(...)
    
    {API} adi_ad9082_adc_ddc_fine_nco_ftw_set(...)
    
    {API} adi_ad9082_adc_ddc_fine_select_set(...)
    FAILED TO WRITE ADC DATA TO SPI REG 0x19, WR->DATA 0x10, RD->DATA 0x0
    
    {SPI} ad9082: w@0019 = 10
    
    {SPI} ad9082: w@0a85 = 00
    
    {SPI} ad9082: w@0a86 = 00
    
    {SPI} ad9082: w@0a87 = 00
    
    {SPI} ad9082: w@0a88 = 00
    
    {SPI} ad9082: w@0a89 = 00
    
    {SPI} ad9082: w@0a8a = 00
    
    {SPI} ad9082: w@0a91 = 00
    
    {SPI} ad9082: w@0a92 = 00
    
    {SPI} ad9082: w@0a93 = 00
    
    {SPI} ad9082: w@0a94 = 00
    
    {SPI} ad9082: w@0a95 = 00
    
    {SPI} ad9082: w@0a96 = 00
    
    {SPI} ad9082: w@0a97 = 00
    
    {SPI} ad9082: w@0a98 = 00
    
    {SPI} ad9082: w@0a99 = 00
    
    {SPI} ad9082: w@0a9a = 00
    
    {SPI} ad9082: w@0a9b = 00
    
    {SPI} ad9082: w@0a9c = 00
    
    {API} adi_ad9082_adc_ddc_fine_overall_dcm_set(...)
    
    {API} adi_ad9082_adc_ddc_fine_select_set(...)
    FAILED TO WRITE ADC DATA TO SPI REG 0x19, WR->DATA 0x10, RD->DATA 0x0
    
    {SPI} ad9082: w@0019 = 10
    FAILED TO WRITE ADC DATA TO SPI REG 0x284, WR->DATA 0x1, RD->DATA 0x0
    
    {SPI} ad9082: w@0284 = 01
    
    {API} adi_ad9082_adc_ddc_fine_dcm_set(...)
    
    {API} adi_ad9082_adc_ddc_fine_select_set(...)
    FAILED TO WRITE ADC DATA TO SPI REG 0x19, WR->DATA 0x20, RD->DATA 0x0
    
    {SPI} ad9082: w@0019 = 20
    
    {SPI} ad9082: r@0287 = 00
    FAILED TO WRITE ADC DATA TO SPI REG 0x287, WR->DATA 0x20, RD->DATA 0x0
    
    {SPI} ad9082: w@0287 = 20
    
    {API} adi_ad9082_adc_ddc_fine_c2r_set(...)
    
    {API} adi_ad9082_adc_ddc_fine_select_set(...)
    FAILED TO WRITE ADC DATA TO SPI REG 0x19, WR->DATA 0x20, RD->DATA 0x0
    
    {SPI} ad9082: w@0019 = 20
    
    {SPI} ad9082: r@0283 = 00
    
    {SPI} ad9082: w@0283 = 00
    
    {API} adi_ad9082_adc_ddc_fine_gain_set(...)
    
    {API} adi_ad9082_adc_ddc_fine_select_set(...)
    FAILED TO WRITE ADC DATA TO SPI REG 0x19, WR->DATA 0x20, RD->DATA 0x0
    
    {SPI} ad9082: w@0019 = 20
    
    {SPI} ad9082: r@0283 = 00
    
    {SPI} ad9082: w@0283 = 00
    
    {API} adi_ad9082_adc_ddc_fine_nco_mode_set(...)
    
    {API} adi_ad9082_adc_ddc_fine_select_set(...)
    FAILED TO WRITE ADC DATA TO SPI REG 0x19, WR->DATA 0x20, RD->DATA 0x0
    
    {SPI} ad9082: w@0019 = 20
    
    {SPI} ad9082: r@0283 = 00
    FAILED TO WRITE ADC DATA TO SPI REG 0x283, WR->DATA 0x40, RD->DATA 0x0
    
    {SPI} ad9082: w@0283 = 40
    
    {API} adi_ad9082_hal_calc_tx_nco_ftw(...)
    
    {API} adi_ad9082_adc_ddc_fine_nco_ftw_set(...)
    
    {API} adi_ad9082_adc_ddc_fine_select_set(...)
    FAILED TO WRITE ADC DATA TO SPI REG 0x19, WR->DATA 0x20, RD->DATA 0x0
    
    {SPI} ad9082: w@0019 = 20
    
    {SPI} ad9082: w@0a85 = 00
    
    {SPI} ad9082: w@0a86 = 00
    
    {SPI} ad9082: w@0a87 = 00
    
    {SPI} ad9082: w@0a88 = 00
    
    {SPI} ad9082: w@0a89 = 00
    
    {SPI} ad9082: w@0a8a = 00
    
    {SPI} ad9082: w@0a91 = 00
    
    {SPI} ad9082: w@0a92 = 00
    
    {SPI} ad9082: w@0a93 = 00
    
    {SPI} ad9082: w@0a94 = 00
    
    {SPI} ad9082: w@0a95 = 00
    
    {SPI} ad9082: w@0a96 = 00
    
    {SPI} ad9082: w@0a97 = 00
    
    {SPI} ad9082: w@0a98 = 00
    
    {SPI} ad9082: w@0a99 = 00
    
    {SPI} ad9082: w@0a9a = 00
    
    {SPI} ad9082: w@0a9b = 00
    
    {SPI} ad9082: w@0a9c = 00
    
    {API} adi_ad9082_adc_ddc_fine_overall_dcm_set(...)
    
    {API} adi_ad9082_adc_ddc_fine_select_set(...)
    FAILED TO WRITE ADC DATA TO SPI REG 0x19, WR->DATA 0x20, RD->DATA 0x0
    
    {SPI} ad9082: w@0019 = 20
    FAILED TO WRITE ADC DATA TO SPI REG 0x284, WR->DATA 0x1, RD->DATA 0x0
    
    {SPI} ad9082: w@0284 = 01
    
    {API} adi_ad9082_jesd_tx_res_sel_set(...)
    
    {API} adi_ad9082_jesd_tx_link_select_set(...)
    FAILED TO WRITE ADC DATA TO SPI REG 0x1A, WR->DATA 0x1, RD->DATA 0x0
    
    {SPI} ad9082: w@001a = 01
    
    {SPI} ad9082: r@02a8 = 00
    FAILED TO WRITE ADC DATA TO SPI REG 0x2A8, WR->DATA 0x4, RD->DATA 0x0
    
    {SPI} ad9082: w@02a8 = 04
    
    {API} adi_ad9082_jesd_tx_link_conv_sel_set(...)
    
    {API} adi_ad9082_jesd_tx_conv_mask_set(...)
    
    {API} adi_ad9082_jesd_tx_link_select_set(...)
    FAILED TO WRITE ADC DATA TO SPI REG 0x1A, WR->DATA 0x1, RD->DATA 0x0
    
    {SPI} ad9082: w@001a = 01
    
    {SPI} ad9082: r@0600 = 00
    
    {SPI} ad9082: w@0600 = 00
    
    {API} adi_ad9082_jesd_tx_conv_mask_set(...)
    
    {API} adi_ad9082_jesd_tx_link_select_set(...)
    FAILED TO WRITE ADC DATA TO SPI REG 0x1A, WR->DATA 0x1, RD->DATA 0x0
    
    {SPI} ad9082: w@001a = 01
    
    {SPI} ad9082: r@0601 = 00
    
    {SPI} ad9082: w@0601 = 00
    
    {API} adi_ad9082_jesd_tx_conv_mask_set(...)
    
    {API} adi_ad9082_jesd_tx_link_select_set(...)
    FAILED TO WRITE ADC DATA TO SPI REG 0x1A, WR->DATA 0x1, RD->DATA 0x0
    
    {SPI} ad9082: w@001a = 01
    
    {SPI} ad9082: r@0602 = 00
    
    {SPI} ad9082: w@0602 = 00
    
    {API} adi_ad9082_jesd_tx_conv_mask_set(...)
    
    {API} adi_ad9082_jesd_tx_link_select_set(...)
    FAILED TO WRITE ADC DATA TO SPI REG 0x1A, WR->DATA 0x1, RD->DATA 0x0
    
    {SPI} ad9082: w@001a = 01
    
    {SPI} ad9082: r@0603 = 00
    
    {SPI} ad9082: w@0603 = 00
    
    {API} adi_ad9082_jesd_tx_conv_mask_set(...)
    
    {API} adi_ad9082_jesd_tx_link_select_set(...)
    FAILED TO WRITE ADC DATA TO SPI REG 0x1A, WR->DATA 0x1, RD->DATA 0x0
    
    {SPI} ad9082: w@001a = 01
    
    {SPI} ad9082: r@0604 = 00
    FAILED TO WRITE ADC DATA TO SPI REG 0x604, WR->DATA 0x80, RD->DATA 0x0
    
    {SPI} ad9082: w@0604 = 80
    
    {API} adi_ad9082_jesd_tx_conv_mask_set(...)
    
    {API} adi_ad9082_jesd_tx_link_select_set(...)
    FAILED TO WRITE ADC DATA TO SPI REG 0x1A, WR->DATA 0x1, RD->DATA 0x0
    
    {SPI} ad9082: w@001a = 01
    
    {SPI} ad9082: r@0605 = 00
    FAILED TO WRITE ADC DATA TO SPI REG 0x605, WR->DATA 0x80, RD->DATA 0x0
    
    {SPI} ad9082: w@0605 = 80
    
    {API} adi_ad9082_jesd_tx_conv_mask_set(...)
    
    {API} adi_ad9082_jesd_tx_link_select_set(...)
    FAILED TO WRITE ADC DATA TO SPI REG 0x1A, WR->DATA 0x1, RD->DATA 0x0
    
    {SPI} ad9082: w@001a = 01
    
    {SPI} ad9082: r@0606 = 00
    FAILED TO WRITE ADC DATA TO SPI REG 0x606, WR->DATA 0x80, RD->DATA 0x0
    
    {SPI} ad9082: w@0606 = 80
    
    {API} adi_ad9082_jesd_tx_conv_mask_set(...)
    
    {API} adi_ad9082_jesd_tx_link_select_set(...)
    FAILED TO WRITE ADC DATA TO SPI REG 0x1A, WR->DATA 0x1, RD->DATA 0x0
    
    {SPI} ad9082: w@001a = 01
    
    {SPI} ad9082: r@0607 = 00
    FAILED TO WRITE ADC DATA TO SPI REG 0x607, WR->DATA 0x80, RD->DATA 0x0
    
    {SPI} ad9082: w@0607 = 80
    
    {API} adi_ad9082_jesd_tx_conv_mask_set(...)
    
    {API} adi_ad9082_jesd_tx_link_select_set(...)
    FAILED TO WRITE ADC DATA TO SPI REG 0x1A, WR->DATA 0x1, RD->DATA 0x0
    
    {SPI} ad9082: w@001a = 01
    
    {SPI} ad9082: r@0608 = 00
    FAILED TO WRITE ADC DATA TO SPI REG 0x608, WR->DATA 0x80, RD->DATA 0x0
    
    {SPI} ad9082: w@0608 = 80
    
    {API} adi_ad9082_jesd_tx_conv_mask_set(...)
    
    {API} adi_ad9082_jesd_tx_link_select_set(...)
    FAILED TO WRITE ADC DATA TO SPI REG 0x1A, WR->DATA 0x1, RD->DATA 0x0
    
    {SPI} ad9082: w@001a = 01
    
    {SPI} ad9082: r@0609 = 00
    FAILED TO WRITE ADC DATA TO SPI REG 0x609, WR->DATA 0x80, RD->DATA 0x0
    
    {SPI} ad9082: w@0609 = 80
    
    {API} adi_ad9082_jesd_tx_conv_mask_set(...)
    
    {API} adi_ad9082_jesd_tx_link_select_set(...)
    FAILED TO WRITE ADC DATA TO SPI REG 0x1A, WR->DATA 0x1, RD->DATA 0x0
    
    {SPI} ad9082: w@001a = 01
    
    {SPI} ad9082: r@060a = 00
    FAILED TO WRITE ADC DATA TO SPI REG 0x60A, WR->DATA 0x80, RD->DATA 0x0
    
    {SPI} ad9082: w@060a = 80
    
    {API} adi_ad9082_jesd_tx_conv_mask_set(...)
    
    {API} adi_ad9082_jesd_tx_link_select_set(...)
    FAILED TO WRITE ADC DATA TO SPI REG 0x1A, WR->DATA 0x1, RD->DATA 0x0
    
    {SPI} ad9082: w@001a = 01
    
    {SPI} ad9082: r@060b = 00
    FAILED TO WRITE ADC DATA TO SPI REG 0x60B, WR->DATA 0x80, RD->DATA 0x0
    
    {SPI} ad9082: w@060b = 80
    
    {API} adi_ad9082_jesd_tx_conv_mask_set(...)
    
    {API} adi_ad9082_jesd_tx_link_select_set(...)
    FAILED TO WRITE ADC DATA TO SPI REG 0x1A, WR->DATA 0x1, RD->DATA 0x0
    
    {SPI} ad9082: w@001a = 01
    
    {SPI} ad9082: r@060c = 00
    FAILED TO WRITE ADC DATA TO SPI REG 0x60C, WR->DATA 0x80, RD->DATA 0x0
    
    {SPI} ad9082: w@060c = 80
    
    {API} adi_ad9082_jesd_tx_conv_mask_set(...)
    
    {API} adi_ad9082_jesd_tx_link_select_set(...)
    FAILED TO WRITE ADC DATA TO SPI REG 0x1A, WR->DATA 0x1, RD->DATA 0x0
    
    {SPI} ad9082: w@001a = 01
    
    {SPI} ad9082: r@060d = 00
    FAILED TO WRITE ADC DATA TO SPI REG 0x60D, WR->DATA 0x80, RD->DATA 0x0
    
    {SPI} ad9082: w@060d = 80
    
    {API} adi_ad9082_jesd_tx_conv_mask_set(...)
    
    {API} adi_ad9082_jesd_tx_link_select_set(...)
    FAILED TO WRITE ADC DATA TO SPI REG 0x1A, WR->DATA 0x1, RD->DATA 0x0
    
    {SPI} ad9082: w@001a = 01
    
    {SPI} ad9082: r@060e = 00
    FAILED TO WRITE ADC DATA TO SPI REG 0x60E, WR->DATA 0x80, RD->DATA 0x0
    
    {SPI} ad9082: w@060e = 80
    
    {API} adi_ad9082_jesd_tx_conv_mask_set(...)
    
    {API} adi_ad9082_jesd_tx_link_select_set(...)
    FAILED TO WRITE ADC DATA TO SPI REG 0x1A, WR->DATA 0x1, RD->DATA 0x0
    
    {SPI} ad9082: w@001a = 01
    
    {SPI} ad9082: r@060f = 00
    FAILED TO WRITE ADC DATA TO SPI REG 0x60F, WR->DATA 0x80, RD->DATA 0x0
    
    {SPI} ad9082: w@060f = 80
    
    {API} adi_ad9082_jesd_tx_conv_sel_set(...)
    
    {API} adi_ad9082_jesd_tx_link_select_set(...)
    FAILED TO WRITE ADC DATA TO SPI REG 0x1A, WR->DATA 0x1, RD->DATA 0x0
    
    {SPI} ad9082: w@001a = 01
    
    {SPI} ad9082: r@0600 = 00
    
    {SPI} ad9082: w@0600 = 00
    
    {SPI} ad9082: r@0640 = 00
    
    {SPI} ad9082: r@0600 = 00
    
    {API} adi_ad9082_adc_ddc_fine_select_set(...)
    FAILED TO WRITE ADC DATA TO SPI REG 0x19, WR->DATA 0x1, RD->DATA 0x0
    
    {SPI} ad9082: w@0019 = 01
    
    {SPI} ad9082: r@0284 = 00
    
    {API} adi_ad9082_adc_chip_dcm_ratio_set(...)
    
    {API} adi_ad9082_jesd_tx_link_select_set(...)
    FAILED TO WRITE ADC DATA TO SPI REG 0x1A, WR->DATA 0x1, RD->DATA 0x0
    
    {SPI} ad9082: w@001a = 01
    
    {SPI} ad9082: w@0289 = 00
    
    {API} adi_ad9082_jesd_tx_conv_sel_set(...)
    
    {API} adi_ad9082_jesd_tx_link_select_set(...)
    FAILED TO WRITE ADC DATA TO SPI REG 0x1A, WR->DATA 0x1, RD->DATA 0x0
    
    {SPI} ad9082: w@001a = 01
    
    {SPI} ad9082: r@0601 = 00
    FAILED TO WRITE ADC DATA TO SPI REG 0x601, WR->DATA 0x2, RD->DATA 0x0
    
    {SPI} ad9082: w@0601 = 02
    
    {SPI} ad9082: r@0640 = 00
    
    {SPI} ad9082: r@0600 = 00
    
    {API} adi_ad9082_adc_ddc_fine_select_set(...)
    FAILED TO WRITE ADC DATA TO SPI REG 0x19, WR->DATA 0x1, RD->DATA 0x0
    
    {SPI} ad9082: w@0019 = 01
    
    {SPI} ad9082: r@0284 = 00
    
    {API} adi_ad9082_adc_chip_dcm_ratio_set(...)
    
    {API} adi_ad9082_jesd_tx_link_select_set(...)
    FAILED TO WRITE ADC DATA TO SPI REG 0x1A, WR->DATA 0x1, RD->DATA 0x0
    
    {SPI} ad9082: w@001a = 01
    
    {SPI} ad9082: w@0289 = 00
    
    {API} adi_ad9082_jesd_tx_conv_sel_set(...)
    
    {API} adi_ad9082_jesd_tx_link_select_set(...)
    FAILED TO WRITE ADC DATA TO SPI REG 0x1A, WR->DATA 0x1, RD->DATA 0x0
    
    {SPI} ad9082: w@001a = 01
    
    {SPI} ad9082: r@0602 = 00
    FAILED TO WRITE ADC DATA TO SPI REG 0x602, WR->DATA 0x8, RD->DATA 0x0
    
    {SPI} ad9082: w@0602 = 08
    
    {SPI} ad9082: r@0640 = 00
    
    {SPI} ad9082: r@0600 = 00
    
    {API} adi_ad9082_adc_ddc_fine_select_set(...)
    FAILED TO WRITE ADC DATA TO SPI REG 0x19, WR->DATA 0x1, RD->DATA 0x0
    
    {SPI} ad9082: w@0019 = 01
    
    {SPI} ad9082: r@0284 = 00
    
    {API} adi_ad9082_adc_chip_dcm_ratio_set(...)
    
    {API} adi_ad9082_jesd_tx_link_select_set(...)
    FAILED TO WRITE ADC DATA TO SPI REG 0x1A, WR->DATA 0x1, RD->DATA 0x0
    
    {SPI} ad9082: w@001a = 01
    
    {SPI} ad9082: w@0289 = 00
    
    {API} adi_ad9082_jesd_tx_conv_sel_set(...)
    
    {API} adi_ad9082_jesd_tx_link_select_set(...)
    FAILED TO WRITE ADC DATA TO SPI REG 0x1A, WR->DATA 0x1, RD->DATA 0x0
    
    {SPI} ad9082: w@001a = 01
    
    {SPI} ad9082: r@0603 = 00
    FAILED TO WRITE ADC DATA TO SPI REG 0x603, WR->DATA 0xA, RD->DATA 0x0
    
    {SPI} ad9082: w@0603 = 0a
    
    {SPI} ad9082: r@0640 = 00
    
    {SPI} ad9082: r@0600 = 00
    
    {API} adi_ad9082_adc_ddc_fine_select_set(...)
    FAILED TO WRITE ADC DATA TO SPI REG 0x19, WR->DATA 0x1, RD->DATA 0x0
    
    {SPI} ad9082: w@0019 = 01
    
    {SPI} ad9082: r@0284 = 00
    
    {API} adi_ad9082_adc_chip_dcm_ratio_set(...)
    
    {API} adi_ad9082_jesd_tx_link_select_set(...)
    FAILED TO WRITE ADC DATA TO SPI REG 0x1A, WR->DATA 0x1, RD->DATA 0x0
    
    {SPI} ad9082: w@001a = 01
    
    {SPI} ad9082: w@0289 = 00
    
    {API} adi_ad9082_jesd_tx_conv_sel_set(...)
    
    {API} adi_ad9082_jesd_tx_link_select_set(...)
    FAILED TO WRITE ADC DATA TO SPI REG 0x1A, WR->DATA 0x1, RD->DATA 0x0
    
    {SPI} ad9082: w@001a = 01
    
    {SPI} ad9082: r@0604 = 00
    FAILED TO WRITE ADC DATA TO SPI REG 0x604, WR->DATA 0xF, RD->DATA 0x0
    
    {SPI} ad9082: w@0604 = 0f
    
    {SPI} ad9082: r@0640 = 00
    
    {SPI} ad9082: r@0600 = 00
    
    {API} adi_ad9082_adc_ddc_fine_select_set(...)
    FAILED TO WRITE ADC DATA TO SPI REG 0x19, WR->DATA 0x1, RD->DATA 0x0
    
    {SPI} ad9082: w@0019 = 01
    
    {SPI} ad9082: r@0284 = 00
    
    {API} adi_ad9082_adc_chip_dcm_ratio_set(...)
    
    {API} adi_ad9082_jesd_tx_link_select_set(...)
    FAILED TO WRITE ADC DATA TO SPI REG 0x1A, WR->DATA 0x1, RD->DATA 0x0
    
    {SPI} ad9082: w@001a = 01
    
    {SPI} ad9082: w@0289 = 00
    
    {API} adi_ad9082_jesd_tx_conv_sel_set(...)
    
    {API} adi_ad9082_jesd_tx_link_select_set(...)
    FAILED TO WRITE ADC DATA TO SPI REG 0x1A, WR->DATA 0x1, RD->DATA 0x0
    
    {SPI} ad9082: w@001a = 01
    
    {SPI} ad9082: r@0605 = 00
    FAILED TO WRITE ADC DATA TO SPI REG 0x605, WR->DATA 0xF, RD->DATA 0x0
    
    {SPI} ad9082: w@0605 = 0f
    
    {SPI} ad9082: r@0640 = 00
    
    {SPI} ad9082: r@0600 = 00
    
    {API} adi_ad9082_adc_ddc_fine_select_set(...)
    FAILED TO WRITE ADC DATA TO SPI REG 0x19, WR->DATA 0x1, RD->DATA 0x0
    
    {SPI} ad9082: w@0019 = 01
    
    {SPI} ad9082: r@0284 = 00
    
    {API} adi_ad9082_adc_chip_dcm_ratio_set(...)
    
    {API} adi_ad9082_jesd_tx_link_select_set(...)
    FAILED TO WRITE ADC DATA TO SPI REG 0x1A, WR->DATA 0x1, RD->DATA 0x0
    
    {SPI} ad9082: w@001a = 01
    
    {SPI} ad9082: w@0289 = 00
    
    {API} adi_ad9082_jesd_tx_conv_sel_set(...)
    
    {API} adi_ad9082_jesd_tx_link_select_set(...)
    FAILED TO WRITE ADC DATA TO SPI REG 0x1A, WR->DATA 0x1, RD->DATA 0x0
    
    {SPI} ad9082: w@001a = 01
    
    {SPI} ad9082: r@0606 = 00
    FAILED TO WRITE ADC DATA TO SPI REG 0x606, WR->DATA 0xF, RD->DATA 0x0
    
    {SPI} ad9082: w@0606 = 0f
    
    {SPI} ad9082: r@0640 = 00
    
    {SPI} ad9082: r@0600 = 00
    
    {API} adi_ad9082_adc_ddc_fine_select_set(...)
    FAILED TO WRITE ADC DATA TO SPI REG 0x19, WR->DATA 0x1, RD->DATA 0x0
    
    {SPI} ad9082: w@0019 = 01
    
    {SPI} ad9082: r@0284 = 00
    
    {API} adi_ad9082_adc_chip_dcm_ratio_set(...)
    
    {API} adi_ad9082_jesd_tx_link_select_set(...)
    FAILED TO WRITE ADC DATA TO SPI REG 0x1A, WR->DATA 0x1, RD->DATA 0x0
    
    {SPI} ad9082: w@001a = 01
    
    {SPI} ad9082: w@0289 = 00
    
    {API} adi_ad9082_jesd_tx_conv_sel_set(...)
    
    {API} adi_ad9082_jesd_tx_link_select_set(...)
    FAILED TO WRITE ADC DATA TO SPI REG 0x1A, WR->DATA 0x1, RD->DATA 0x0
    
    {SPI} ad9082: w@001a = 01
    
    {SPI} ad9082: r@0607 = 00
    FAILED TO WRITE ADC DATA TO SPI REG 0x607, WR->DATA 0xF, RD->DATA 0x0
    
    {SPI} ad9082: w@0607 = 0f
    
    {SPI} ad9082: r@0640 = 00
    
    {SPI} ad9082: r@0600 = 00
    
    {API} adi_ad9082_adc_ddc_fine_select_set(...)
    FAILED TO WRITE ADC DATA TO SPI REG 0x19, WR->DATA 0x1, RD->DATA 0x0
    
    {SPI} ad9082: w@0019 = 01
    
    {SPI} ad9082: r@0284 = 00
    
    {API} adi_ad9082_adc_chip_dcm_ratio_set(...)
    
    {API} adi_ad9082_jesd_tx_link_select_set(...)
    FAILED TO WRITE ADC DATA TO SPI REG 0x1A, WR->DATA 0x1, RD->DATA 0x0
    
    {SPI} ad9082: w@001a = 01
    
    {SPI} ad9082: w@0289 = 00
    
    {API} adi_ad9082_jesd_tx_conv_sel_set(...)
    
    {API} adi_ad9082_jesd_tx_link_select_set(...)
    FAILED TO WRITE ADC DATA TO SPI REG 0x1A, WR->DATA 0x1, RD->DATA 0x0
    
    {SPI} ad9082: w@001a = 01
    
    {SPI} ad9082: r@0608 = 00
    FAILED TO WRITE ADC DATA TO SPI REG 0x608, WR->DATA 0xF, RD->DATA 0x0
    
    {SPI} ad9082: w@0608 = 0f
    
    {SPI} ad9082: r@0640 = 00
    
    {SPI} ad9082: r@0600 = 00
    
    {API} adi_ad9082_adc_ddc_fine_select_set(...)
    FAILED TO WRITE ADC DATA TO SPI REG 0x19, WR->DATA 0x1, RD->DATA 0x0
    
    {SPI} ad9082: w@0019 = 01
    
    {SPI} ad9082: r@0284 = 00
    
    {API} adi_ad9082_adc_chip_dcm_ratio_set(...)
    
    {API} adi_ad9082_jesd_tx_link_select_set(...)
    FAILED TO WRITE ADC DATA TO SPI REG 0x1A, WR->DATA 0x1, RD->DATA 0x0
    
    {SPI} ad9082: w@001a = 01
    
    {SPI} ad9082: w@0289 = 00
    
    {API} adi_ad9082_jesd_tx_conv_sel_set(...)
    
    {API} adi_ad9082_jesd_tx_link_select_set(...)
    FAILED TO WRITE ADC DATA TO SPI REG 0x1A, WR->DATA 0x1, RD->DATA 0x0
    
    {SPI} ad9082: w@001a = 01
    
    {SPI} ad9082: r@0609 = 00
    FAILED TO WRITE ADC DATA TO SPI REG 0x609, WR->DATA 0xF, RD->DATA 0x0
    
    {SPI} ad9082: w@0609 = 0f
    
    {SPI} ad9082: r@0640 = 00
    
    {SPI} ad9082: r@0600 = 00
    
    {API} adi_ad9082_adc_ddc_fine_select_set(...)
    FAILED TO WRITE ADC DATA TO SPI REG 0x19, WR->DATA 0x1, RD->DATA 0x0
    
    {SPI} ad9082: w@0019 = 01
    
    {SPI} ad9082: r@0284 = 00
    
    {API} adi_ad9082_adc_chip_dcm_ratio_set(...)
    
    {API} adi_ad9082_jesd_tx_link_select_set(...)
    FAILED TO WRITE ADC DATA TO SPI REG 0x1A, WR->DATA 0x1, RD->DATA 0x0
    
    {SPI} ad9082: w@001a = 01
    
    {SPI} ad9082: w@0289 = 00
    
    {API} adi_ad9082_jesd_tx_conv_sel_set(...)
    
    {API} adi_ad9082_jesd_tx_link_select_set(...)
    FAILED TO WRITE ADC DATA TO SPI REG 0x1A, WR->DATA 0x1, RD->DATA 0x0
    
    {SPI} ad9082: w@001a = 01
    
    {SPI} ad9082: r@060a = 00
    FAILED TO WRITE ADC DATA TO SPI REG 0x60A, WR->DATA 0xF, RD->DATA 0x0
    
    {SPI} ad9082: w@060a = 0f
    
    {SPI} ad9082: r@0640 = 00
    
    {SPI} ad9082: r@0600 = 00
    
    {API} adi_ad9082_adc_ddc_fine_select_set(...)
    FAILED TO WRITE ADC DATA TO SPI REG 0x19, WR->DATA 0x1, RD->DATA 0x0
    
    {SPI} ad9082: w@0019 = 01
    
    {SPI} ad9082: r@0284 = 00
    
    {API} adi_ad9082_adc_chip_dcm_ratio_set(...)
    
    {API} adi_ad9082_jesd_tx_link_select_set(...)
    FAILED TO WRITE ADC DATA TO SPI REG 0x1A, WR->DATA 0x1, RD->DATA 0x0
    
    {SPI} ad9082: w@001a = 01
    
    {SPI} ad9082: w@0289 = 00
    
    {API} adi_ad9082_jesd_tx_conv_sel_set(...)
    
    {API} adi_ad9082_jesd_tx_link_select_set(...)
    FAILED TO WRITE ADC DATA TO SPI REG 0x1A, WR->DATA 0x1, RD->DATA 0x0
    
    {SPI} ad9082: w@001a = 01
    
    {SPI} ad9082: r@060b = 00
    FAILED TO WRITE ADC DATA TO SPI REG 0x60B, WR->DATA 0xF, RD->DATA 0x0
    
    {SPI} ad9082: w@060b = 0f
    
    {SPI} ad9082: r@0640 = 00
    
    {SPI} ad9082: r@0600 = 00
    
    {API} adi_ad9082_adc_ddc_fine_select_set(...)
    FAILED TO WRITE ADC DATA TO SPI REG 0x19, WR->DATA 0x1, RD->DATA 0x0
    
    {SPI} ad9082: w@0019 = 01
    
    {SPI} ad9082: r@0284 = 00
    
    {API} adi_ad9082_adc_chip_dcm_ratio_set(...)
    
    {API} adi_ad9082_jesd_tx_link_select_set(...)
    FAILED TO WRITE ADC DATA TO SPI REG 0x1A, WR->DATA 0x1, RD->DATA 0x0
    
    {SPI} ad9082: w@001a = 01
    
    {SPI} ad9082: w@0289 = 00
    
    {API} adi_ad9082_jesd_tx_conv_sel_set(...)
    
    {API} adi_ad9082_jesd_tx_link_select_set(...)
    FAILED TO WRITE ADC DATA TO SPI REG 0x1A, WR->DATA 0x1, RD->DATA 0x0
    
    {SPI} ad9082: w@001a = 01
    
    {SPI} ad9082: r@060c = 00
    FAILED TO WRITE ADC DATA TO SPI REG 0x60C, WR->DATA 0xF, RD->DATA 0x0
    
    {SPI} ad9082: w@060c = 0f
    
    {SPI} ad9082: r@0640 = 00
    
    {SPI} ad9082: r@0600 = 00
    
    {API} adi_ad9082_adc_ddc_fine_select_set(...)
    FAILED TO WRITE ADC DATA TO SPI REG 0x19, WR->DATA 0x1, RD->DATA 0x0
    
    {SPI} ad9082: w@0019 = 01
    
    {SPI} ad9082: r@0284 = 00
    
    {API} adi_ad9082_adc_chip_dcm_ratio_set(...)
    
    {API} adi_ad9082_jesd_tx_link_select_set(...)
    FAILED TO WRITE ADC DATA TO SPI REG 0x1A, WR->DATA 0x1, RD->DATA 0x0
    
    {SPI} ad9082: w@001a = 01
    
    {SPI} ad9082: w@0289 = 00
    
    {API} adi_ad9082_jesd_tx_conv_sel_set(...)
    
    {API} adi_ad9082_jesd_tx_link_select_set(...)
    FAILED TO WRITE ADC DATA TO SPI REG 0x1A, WR->DATA 0x1, RD->DATA 0x0
    
    {SPI} ad9082: w@001a = 01
    
    {SPI} ad9082: r@060d = 00
    FAILED TO WRITE ADC DATA TO SPI REG 0x60D, WR->DATA 0xF, RD->DATA 0x0
    
    {SPI} ad9082: w@060d = 0f
    
    {SPI} ad9082: r@0640 = 00
    
    {SPI} ad9082: r@0600 = 00
    
    {API} adi_ad9082_adc_ddc_fine_select_set(...)
    FAILED TO WRITE ADC DATA TO SPI REG 0x19, WR->DATA 0x1, RD->DATA 0x0
    
    {SPI} ad9082: w@0019 = 01
    
    {SPI} ad9082: r@0284 = 00
    
    {API} adi_ad9082_adc_chip_dcm_ratio_set(...)
    
    {API} adi_ad9082_jesd_tx_link_select_set(...)
    FAILED TO WRITE ADC DATA TO SPI REG 0x1A, WR->DATA 0x1, RD->DATA 0x0
    
    {SPI} ad9082: w@001a = 01
    
    {SPI} ad9082: w@0289 = 00
    
    {API} adi_ad9082_jesd_tx_conv_sel_set(...)
    
    {API} adi_ad9082_jesd_tx_link_select_set(...)
    FAILED TO WRITE ADC DATA TO SPI REG 0x1A, WR->DATA 0x1, RD->DATA 0x0
    
    {SPI} ad9082: w@001a = 01
    
    {SPI} ad9082: r@060e = 00
    FAILED TO WRITE ADC DATA TO SPI REG 0x60E, WR->DATA 0xF, RD->DATA 0x0
    
    {SPI} ad9082: w@060e = 0f
    
    {SPI} ad9082: r@0640 = 00
    
    {SPI} ad9082: r@0600 = 00
    
    {API} adi_ad9082_adc_ddc_fine_select_set(...)
    FAILED TO WRITE ADC DATA TO SPI REG 0x19, WR->DATA 0x1, RD->DATA 0x0
    
    {SPI} ad9082: w@0019 = 01
    
    {SPI} ad9082: r@0284 = 00
    
    {API} adi_ad9082_adc_chip_dcm_ratio_set(...)
    
    {API} adi_ad9082_jesd_tx_link_select_set(...)
    FAILED TO WRITE ADC DATA TO SPI REG 0x1A, WR->DATA 0x1, RD->DATA 0x0
    
    {SPI} ad9082: w@001a = 01
    
    {SPI} ad9082: w@0289 = 00
    
    {API} adi_ad9082_jesd_tx_conv_sel_set(...)
    
    {API} adi_ad9082_jesd_tx_link_select_set(...)
    FAILED TO WRITE ADC DATA TO SPI REG 0x1A, WR->DATA 0x1, RD->DATA 0x0
    
    {SPI} ad9082: w@001a = 01
    
    {SPI} ad9082: r@060f = 00
    FAILED TO WRITE ADC DATA TO SPI REG 0x60F, WR->DATA 0xF, RD->DATA 0x0
    
    {SPI} ad9082: w@060f = 0f
    
    {SPI} ad9082: r@0640 = 00
    
    {SPI} ad9082: r@0600 = 00
    
    {API} adi_ad9082_adc_ddc_fine_select_set(...)
    FAILED TO WRITE ADC DATA TO SPI REG 0x19, WR->DATA 0x1, RD->DATA 0x0
    
    {SPI} ad9082: w@0019 = 01
    
    {SPI} ad9082: r@0284 = 00
    
    {API} adi_ad9082_adc_chip_dcm_ratio_set(...)
    
    {API} adi_ad9082_jesd_tx_link_select_set(...)
    FAILED TO WRITE ADC DATA TO SPI REG 0x1A, WR->DATA 0x1, RD->DATA 0x0
    
    {SPI} ad9082: w@001a = 01
    
    {SPI} ad9082: w@0289 = 00
    
    {API} adi_ad9082_jesd_tx_link_config_set(...)
    
    {API} adi_ad9082_jesd_tx_link_select_set(...)
    FAILED TO WRITE ADC DATA TO SPI REG 0x1A, WR->DATA 0x1, RD->DATA 0x0
    
    {SPI} ad9082: w@001a = 01
    
    {SPI} ad9082: r@0289 = 00
    
    {ERROR} chip decimation is 0.
    APP: ad9082 Rx Path Configuration Error
    
    *
    
    

    The JESD and ANALOG CLOCK settings are attached as CODE_SETTINGS.xlsx.

    XLSX

    Yes we are using internal PLL.

    what might be the reason that when API accesses few registers the SPI bus stops responding ?

    125MHz with 50mV clock signal was observed on SYSREF_P on ADC9082 add on card.

    The code for running UC22 is as follows:

    int32_t runApiUseCase(int32_t uc)
    {
    	int32_t err, i, use_7044 = 0, use_ce_brd = 1;
    	uint64_t hmc7044_crystal_input = 122.88e6;
    
    //	uc = 0;
    	use_7044 = 1;
    	use_ce_brd = 1;
    
    	/* print use case info */
    	if (uc >= 0)
    	{
    		printf("Running uc%d ", uc);
    		printf(use_ce_brd > 0 ? "on CE board " : "on PE board ");
    		printf(use_7044 > 0 ? "using hmc7044.\r\n" : "using direct clk.\r\n");
    	}
    	else if (uc < -1)
    	{
    		printf("Usage: ad9082_app [uc] [use_7044] [use_ce_brd]:\r\n");
    		return API_CMS_ERROR_OK;
    	}
    
    	/* connect to platform */
    	init_hmc_api();
    	init_adc_api_Structure();
    	init_jesd_param();
    
    	/* show link status only */
    	if (uc == -1)
    	{
    		err = app_show_link_status(&adcDev);
    		printf("\r\n");
    		return API_CMS_ERROR_OK;
    	}
    
    	/* show connected device board info */
    	hmc7044_crystal_input = 100e6;
    	printf("On board crystal select: %6.2fMHz\r\n",
    			(hmc7044_crystal_input / 1.0e6));
    
    	/* show api version */
    	uint8_t ad9082_rev[3];
    	if (err = adi_ad9082_device_api_revision_get(&adcDev, &ad9082_rev[0],
    			&ad9082_rev[1], &ad9082_rev[2]), err != API_CMS_ERROR_OK)
    		return err;
    	printf("AD9082 API v%d.%d.%d\r\n", ad9082_rev[0], ad9082_rev[1],
    			ad9082_rev[2]);
    
    	/* show fpga version */
    	printf("FPGA Image MY OWN \r\n");
    	printf(
    			"APP: Configure Usecase:%d, Tx Path: DAC Clk: %lld, JESD Rx Mode: %d & Rx Path: ADC CLK: %lld, Jesdmode Tx Mode: %d ",
    			uc, clk_hz[uc][2], jrx_param[uc].jesd_mode_id, clk_hz[uc][3],
    			jtx_param[uc][0].jesd_mode_id);
    	{/* Do Hard Rest of Devices*/
    		adi_ad9082_device_reset(&adcDev, AD9082_HARD_RESET);
    	}
    	{ /* setup reference clock */
    		printf("APP: Configure Platform Reference Clocks\r\n");
    		if (use_7044 == 0)
    		{ /* set clock path to use external reference */
    			if (err = adi_ads9_ad9528_vcxo_select_set(0), err
    					!= API_CMS_ERROR_OK)
    				return err;
    			if (err = adi_ads9_mgt_ref_clk_select_set(0), err
    					!= API_CMS_ERROR_OK)
    				return err;
    			if (err = adi_ads9_gbl_clk_select_set(0), err != API_CMS_ERROR_OK)
    				return err;
    		}
    		else
    		{ /* configure 7044 to generate clock */
    			uint64_t ad9082_clk = clk_hz[uc][0], fpga_clk = clk_hz[uc][1];
    			/*Configure FPGA to Use FMC CLKs*/
    			uint32_t reg_val;
    //			ads9_axi_reg_read32(0x942, &reg_val);
    //			ads9_axi_reg_write32(0x942, (reg_val & 0xffff) | 0x20000);
    //			if (err = adi_ads9_mgt_ref_clk_select_set(1), err
    //					!= API_CMS_ERROR_OK)
    //				return err;
    //			if (err = adi_ads9_gbl_clk_select_set(1), err != API_CMS_ERROR_OK)
    //				return err;
    			/*Configure HMC7044 to Provide Clocks For Txfe & FPGA*/
    			uint8_t hmc_priority[] =
    			{ 1, 0, 2, 3 };
    			uint16_t hmc_out_ch = HMC7044_OP_CH_0 | HMC7044_OP_CH_2
    					| HMC7044_OP_CH_3 | HMC7044_OP_CH_6 | HMC7044_OP_CH_8
    					| HMC7044_OP_CH_10 | HMC7044_OP_CH_12 | HMC7044_OP_CH_13;
    			uint64_t hmc_out_204b[14] =
    			{ fpga_clk / 2, 0, ad9082_clk, fpga_clk / 16, 0, 0, fpga_clk / 2, 0,
    					fpga_clk, 0, fpga_clk / 2, 0, fpga_clk, fpga_clk / 16 };
    			uint64_t hmc_out_204c[14] =
    			{ fpga_clk, 0, ad9082_clk, fpga_clk / 32, 0, 0, fpga_clk, 0,
    					fpga_clk, 0, fpga_clk, 0, fpga_clk, fpga_clk / 32 };
    			if (((jrx_param[uc].jesd_jesdv == 2)
    					|| (jtx_param[uc][0].jesd_jesdv == 2))
    					&& (fpga_clk * 66 < 8.3e9))
    			{ /* double fpga refclk for 204C lane rate < 8.3Gbps */
    				hmc_out_204c[8] *= 2;
    				hmc_out_204c[12] *= 2;
    			}
    			if (err = adi_hmc7044_device_init(&hmc7044_dev), err
    					!= API_CMS_ERROR_OK)
    				return err;
    			if (err = adi_hmc7044_device_reset(&hmc7044_dev, 0), err
    					!= API_CMS_ERROR_OK)
    				return err;
    			/*Disable Configure but Output Drivers Prior to Clocking Scheme Configuration*/
    
    			for (i = 0; i < HMC7044_NOF_OP_CH; i++)
    			{
    				if (err = adi_hmc7044_output_config_set(&hmc7044_dev, i,
    						HMC7044_OP_SIG_CH_DIV, 0, 0, 0), err != API_CMS_ERROR_OK)
    					return err;
    			}
    			if (err = adi_hmc7044_input_reference_set(&hmc7044_dev, 0,
    					IPBUFFER_INTERNAL_100_OHM_EN | IPBUFFER_AC_COUPLED_MODE_EN,
    					1), err != API_CMS_ERROR_OK)
    				return err;
    			if (err = adi_hmc7044_input_reference_set(&hmc7044_dev, 1,
    					IPBUFFER_INTERNAL_100_OHM_EN | IPBUFFER_AC_COUPLED_MODE_EN,
    					1), err != API_CMS_ERROR_OK)
    				return err;
    			if (err = adi_hmc7044_input_reference_los_config_set(&hmc7044_dev,
    					7, 0, 0), err != API_CMS_ERROR_OK)
    				return err;
    			if (err = adi_hmc7044_vco_sel_set(&hmc7044_dev,
    					HMC7044_VCO_INTERNAL_3GHZ, 0), err != API_CMS_ERROR_OK)
    				return err;
    			if (err = adi_hmc7044_output_sync_config_set(&hmc7044_dev, 3, 0, 1,
    					1), err != API_CMS_ERROR_OK) /* clkout3 as async mode */
    				return err;
    			if (err = adi_hmc7044_output_sync_config_set(&hmc7044_dev, 13, 0, 1,
    					1), err != API_CMS_ERROR_OK) /* clkout13 as async mode */
    				return err;
    			if (err = adi_hmc7044_output_multi_slip_config_set(&hmc7044_dev, 13,
    					0, 0), err != API_CMS_ERROR_OK)
    				return err;
    			if (err = adi_hmc7044_reg_update(&hmc7044_dev), err
    					!= API_CMS_ERROR_OK)
    				return err;
    			if (err = adi_hmc7044_clk_config(&hmc7044_dev, HMC7044_CLK_IN_0,
    					hmc_priority, hmc7044_crystal_input, hmc7044_crystal_input,
    					hmc_out_ch,
    					((jrx_param[uc].jesd_jesdv == 2)
    							|| (jtx_param[uc][0].jesd_jesdv == 2)) ?
    							(hmc_out_204c) : (hmc_out_204b)), err
    					!= API_CMS_ERROR_OK)
    			{
    				if (err == API_CMS_ERROR_INVALID_PARAM)
    					printf("APP: HMC7044: Invalid param passed.\r\n");
    				return err;
    			}
    			if (err = adi_hmc7044_reg_update(&hmc7044_dev), err
    					!= API_CMS_ERROR_OK)
    				return err;
    			usleep(100000);
    //			if (err = ads9_wait_us(NULL, 100000), err != API_CMS_ERROR_OK)
    //				return err;
    			uint8_t hmc_pll_locked = 0;
    			if (err = adi_hmc7044_device_pll_lock_status_get(&hmc7044_dev,
    					&hmc_pll_locked), err != API_CMS_ERROR_OK)
    			{
    				printf("APP: HMC7044: PLL is not locked.\r\n");
    				return err;
    			}
    		}
    		printf("APP: Reference Clocks Configured\r\n");
    	}
    	/* ADS9 FPGA  JESD Interface and Data & Playback Configuration Sequenece
    	 *  Do FPGA JESD Rx and Tx Interface Parameter Configuration
    	 *       adi_ads9_config_jesd
    	 *  DO FPGA RAM Assignment for Playback of Vector  Data and Captured Data
    	 *       adi_ads9_capture_size_set
    	 *       adi_ads9_pattern_addr_set
    	 *       adi_ads9_pattern_len_set
    	 * DO  FPGA Clock Configuration
    	 *
    	 *
    	 */
    	if (uc > 0)
    	{ /* setup fpga jesd params */
    		printf("APP: Configure FPGA JESD Interfaces\r\n");
    		if (err = adi_ads9_config_jesd(jtx_param[uc], &jrx_param[uc]), err
    				!= API_CMS_ERROR_OK)
    			return err;
    		if (err = adi_ads9_capture_size_set(0x20), err != API_CMS_ERROR_OK)
    			return err;
    		if (err = adi_ads9_pattern_addr_set(0x80000000), err != API_CMS_ERROR_OK)
    			return err;
    		if (err = adi_ads9_pattern_len_set(0x8000), err != API_CMS_ERROR_OK)
    			return err;
    		uint32_t ads9_link_clk_div =
    				(((jrx_param[uc].jesd_jesdv == 2)
    						|| (jtx_param[uc][0].jesd_jesdv == 2))
    						&& (clk_hz[uc][1] * 66 < 8.3e9)) ? 0x101 : 0x000;
    		if (err = adi_ads9_reg_set(0x10c, ads9_link_clk_div), err
    				!= API_CMS_ERROR_OK) /* line_rate_rx_ctrl */
    			return err;
    		if (err = adi_ads9_reg_set(0x50c, ads9_link_clk_div), err
    				!= API_CMS_ERROR_OK) /* line_rate_tx_ctrl */
    			return err;
    		if (err = adi_ads9_reg_set(0x540, 1), err != API_CMS_ERROR_OK) /* transmit_skip_data = 1 */
    			return err;
    		if (err = adi_ads9_reg_set(0x106, 0x000), err != API_CMS_ERROR_OK) /* skip_rx_link_init = 0 */
    			return err;
    		if (err = adi_ads9_reg_set(0x947, 2), err != API_CMS_ERROR_OK) /* bidir_start = 1 */
    			return err;
    		if (err = adi_ads9_reg_set(0x106, 0x400), err != API_CMS_ERROR_OK) /* skip_rx_link_init = 1 */
    			return err;
    		if ((jrx_param[uc].jesd_l > 0) && (jrx_param[uc].jesd_jesdv == 2)
    				&& ((clk_hz[uc][1] * 66) > AD9082_JESDRX_204C_CAL_THRESH))
    		{
    			if (adi_ads9_jesd_tx_lane_driver_config(0xFF, 0x0, 0x0, 0x14), err
    					!= API_CMS_ERROR_OK)
    			{
    				return err;
    			}
    		}
    		else
    		{
    			if (adi_ads9_jesd_tx_lane_driver_config(0xFF, 0x4, 0x4, 0x1C), err
    					!= API_CMS_ERROR_OK)
    			{
    				return err;
    			}
    		}
    		printf("APP: FPGA JESD Interfaces Configured\r\n");
    	}
    	/* AD9082 Device Data Path Configuration Sequenece
    	 *  Do AD9082 Device RESET, adi_ad9082_device_reset
    	 *  Do AD9082 Device Initialization: adi_ad9082_device_init
    	 *  Do AD9082 Device Clocks Config (REF CLK, DAC CLK, ADC Clock):adi_ad9082_device_clk_config_set
    	 *  Do AD9082 Device TX Datapath (JESD RX to DAC) Primary Configuration: adi_ad9082_device_startup_tx
    	 *  Do AD9082 Device Tx Datapath Secondary Configuration as per specific UC rquirements
    	 *       eg  TX Gain APIs
    	 *                     - adi_ad9082_dac_duc_nco_gains_set
    	 *           TX Datapath Customization API:
    	 *                     -adi_ad9082_dac_modulation_mux_mode_set
    	 *                     -adi_ad9082_dac_xbar_set
    	 *           TX Test Modes APIs:
    	 *                     -adi_ad9082_device_startup_nco_test
    	 * Do AD9082 Device RX Datapath (ADC to JESD TX) Primary Configuration: adi_ad9082_device_startup_rx
    	 * Do AD9082 Device Rx Datapath Secondary Configuration as per specific UC rquirements
    	 *            eg: RX Gain APIs:
    	 *                   - adi_ad9082_adc_ddc_fine_gain_set
    	 *              RX Datapath Customization APIs
    	 *                   - adi_ad9082_adc_nyquist_zone_set
    	 *                   - adi_ad9082_adc_xbar_set
    	 *                   - adi_ad9082_jesd_tx_fbw_sel_set
    	 *              RX Test Mode APIs:
    	 *                   - adi_ad9082_jesd_loopback_mode_set
    	 *                   - adi_ad9082_adc_ddc_coarse_nco_mode_set
    	 *
    	 */
    	{
    		uint8_t adc_cddc_xbar, cddc_fddc_xbar;
    		printf("APP: Configure ad9082 Device\r\n");
    
    		/* reset ad9082 */
    		if (err = adi_ad9082_device_reset(&adcDev, AD9082_SOFT_RESET), err
    				!= API_CMS_ERROR_OK)
    		{
    			printf("APP: ad9082 Initialisation Error\r\n");
    			return err;
    		}
    
    		/* init ad9082 */
    		if (err = adi_ad9082_device_init(&ad9082_dev), err != API_CMS_ERROR_OK)
    		{
    			printf("APP: ad9082 Initialisation Error\r\n");
    			return err;
    		}
    
    		/* setup ad9082 clock */
    		err = adi_ad9082_device_clk_config_set(&ad9082_dev, clk_hz[uc][2],
    				clk_hz[uc][3], clk_hz[uc][0]);
    		uint8_t ad9082_pll_locked = 0;
    		adi_ad9082_device_clk_pll_lock_status_get(&ad9082_dev,
    				&ad9082_pll_locked);
    		if (ad9082_pll_locked == 0x3)
    		{
    			printf("APP: ad9082 PLL LOCKED\r\n");
    			adi_ad9082_adc_clk_out_enable_set(&ad9082_dev, 1);
    			adi_ad9082_adc_clk_out_voltage_swing_set(&ad9082_dev, 1000);
    		}
    		if (err != API_CMS_ERROR_OK)
    		{
    			printf("APP: Clock Configration error\r\n");
    			return err;
    		}
    
    #if !defined(AD9207_ID) && !defined(AD9209_ID) 
    		/* nco test case */
    		if (uc == 0)
    		{
    			if (err = adi_ad9082_device_startup_nco_test(&ad9082_dev,
    					tx_interp[uc][0], tx_interp[uc][1], tx_dac_chan_xbar[uc],
    					tx_main_shift[uc], tx_chan_shift[uc],
    					(uint16_t) pow(10, ((0 + 20 * log10(0x5a82)) / 20))), err
    					!= API_CMS_ERROR_OK)
    				return err;
    		}
    #endif
    
    #if !defined(AD9207_ID) && !defined(AD9209_ID) 
    		switch (uc)
    		{
    		case 0:
    		case 18:
    		case 22:
    		case 29:
    		case 32:
    			break; /* Rx Only Cases */
    		default:
    			/* start ad9082 tx */
    			if (err = adi_ad9082_device_startup_tx(&ad9082_dev,
    					tx_interp[uc][0], tx_interp[uc][1], tx_dac_chan_xbar[uc],
    					tx_main_shift[uc], tx_chan_shift[uc], &jrx_param[uc]), err
    					!= API_CMS_ERROR_OK)
    			{
    				printf("APP: ad9082 Tx  Path Configuration Error \r\n");
    				if (err == API_CMS_ERROR_JESD_PLL_NOT_LOCKED)
    				{
    					printf(
    							"APP: ad9082 Tx  Path Configuration JESD PLL Not Locked \r\n");
    				}
    				return err;
    			}
    			/* Setup ad9082 tx channel gain */
    			uint16_t tx_chan_gains[8];
    			for (i = 0; i < 8; i++)
    				tx_chan_gains[i] = (uint16_t) (pow(2, 11)
    						* pow(10, (tx_chan_gain[uc][i]) / 20.0));
    			if (err = adi_ad9082_dac_duc_nco_gains_set(&ad9082_dev,
    					tx_chan_gains), err != API_CMS_ERROR_OK)
    				return err;
    		}
    
    		/* Application/Usecase Specific Customization if Required*/
    		switch (uc)
    		{
    		case 19:
    		case 20:
    			/*Select Main CDUC0/1->DAC0, CDUC2/3->DAC2 */
    			if (err = adi_ad9082_dac_modulation_mux_mode_set(&ad9082_dev,
    					AD9082_DAC_PAIR_ALL, AD9082_DAC_MUX_MODE_3), err
    					!= API_CMS_ERROR_OK)
    				return err;
    			break;
    		case 34:
    			/*Route second IQ pair from virtual converters to DAC2
    			 * Select Modulation Mux Mode to DAC0 => I0, DAC1 =>Q0
    			 */
    			if (err = adi_ad9082_dac_xbar_set(&ad9082_dev, AD9082_DAC_2,
    					AD9082_DAC_1), err != API_CMS_ERROR_OK)
    				return err;
    			if (err = adi_ad9082_dac_modulation_mux_mode_set(&ad9082_dev,
    					AD9082_DAC_PAIR_ALL, AD9082_DAC_MUX_MODE_2), err
    					!= API_CMS_ERROR_OK)
    				return err;
    			break;
    		default:
    			/*Use Default Muxing as per SDUG*/
    			break;
    		}
    
    #endif
    		/*Configure Primary Rx Datapath Settings*/
    		switch (uc)
    		{
    		case 0:
    		case 17:
    		case 28:
    		case 35:
    			/*DO NOT Configure as these are TX Only Modes*/
    			break;
    		default:
    			if (err = adi_ad9082_device_startup_rx(&ad9082_dev, rx_cddc_select,
    					rx_fddc_select[uc], rx_cddc_shift[uc], rx_fddc_shift[uc],
    					rx_cddc_dcm[uc], rx_fddc_dcm[uc], rx_cddc_c2r[uc],
    					rx_fddc_c2r, jtx_param[uc], jtx_conv_sel[uc]), err
    					!= API_CMS_ERROR_OK)
    			{
    				printf("APP: ad9082 Rx Path Configuration Error \r\n");
    				return err;
    			}
    		}
    		/* Set gain settings as per Application Usecase */
    		switch (uc)
    		{
    		case 26:
    		case 27:
    			if (err = adi_ad9082_adc_ddc_fine_gain_set(&ad9082_dev,
    					rx_fddc_select[uc], 1), err != API_CMS_ERROR_OK)
    				return err;
    			break;
    		default:
    			break;
    		}
    		/*Enable Internal Loopback Mode*/
    		switch (uc)
    		{
    		case 13:
    		case 26:
    		case 27:
    			/*Internal Loopback Modes*/
    			printf("ad9082: This is loopback usecase \r\n");
    			uint8_t lane_mapping[2][8] =
    			{
    			{ 0, 1, 2, 3, 4, 5, 6, 7 },
    			{ 4, 5, 6, 7, 0, 1, 2, 3 } };
    			if (err = adi_ad9082_jesd_tx_lanes_xbar_set(&ad9082_dev,
    					AD9082_LINK_0, lane_mapping[0]), err != API_CMS_ERROR_OK)
    				return err;
    			if (err = adi_ad9082_jesd_tx_lanes_xbar_set(&ad9082_dev,
    					AD9082_LINK_1, lane_mapping[1]), err != API_CMS_ERROR_OK)
    				return err;
    			if (err = adi_ad9082_jesd_loopback_mode_set(&ad9082_dev, 1), err
    					!= API_CMS_ERROR_OK)
    				return err;
    		default:
    			break;
    
    		}
    		/*Override NCO Mode*/
    		switch (uc)
    		{
    		case 15:
    			if (err = adi_ad9082_adc_ddc_coarse_nco_mode_set(&ad9082_dev,
    					rx_cddc_select, AD9082_ADC_NCO_ZIF), err != API_CMS_ERROR_OK)
    				return err;
    			break;
    		case 26:
    		case 27:
    			/*Enable NCO TEST Mode*/
    			if (err = adi_ad9082_adc_ddc_coarse_nco_mode_set(&ad9082_dev,
    					rx_cddc_select, AD9082_ADC_NCO_TEST), err
    					!= API_CMS_ERROR_OK)
    				return err;
    			break;
    		default:
    			break;
    		}
    
    		/* Override/Customize Default Xbar Settings*/
    		switch (uc)
    		{
    		case 19:
    		case 20:
    			adc_cddc_xbar = AD9082_ADC_2_ADC_REAL_MODE; /* ADC0->CDDC0/2, ADC1-> CDDC1/3 */
    			cddc_fddc_xbar = AD9082_ADC_CDDC0_TO_FDDC0
    					| AD9082_ADC_CDDC0_TO_FDDC1 | AD9082_ADC_CDDC1_TO_FDDC2
    					| AD9082_ADC_CDDC1_TO_FDDC3;
    			cddc_fddc_xbar |= AD9082_ADC_CDDC2_TO_FDDC4
    					| AD9082_ADC_CDDC2_TO_FDDC5 | AD9082_ADC_CDDC3_TO_FDDC6
    					| AD9082_ADC_CDDC3_TO_FDDC7;
    			if (err = adi_ad9082_adc_xbar_set(&ad9082_dev, adc_cddc_xbar,
    					cddc_fddc_xbar), err != API_CMS_ERROR_OK)
    				return err;
    			break;
    		default:
    			break;
    		}
    		/* Enable Full Bandwith Modes as Application Use Case*/
    		switch (uc)
    		{
    		case 22:
    			if (err = adi_ad9082_jesd_tx_fbw_sel_set(&ad9082_dev, AD9082_LINK_0,
    					0x55), err != API_CMS_ERROR_OK)
    				return err;
    			break;
    		default:
    			break;
    		}
    
    		/* Set ADC Nyquist Zone as per Application Usecase for ADC optimal Background Cal Operation*/
    		switch (uc)
    		{
    		case 26:
    		case 27:/*ADC Test Test Mode*/
    			if (err = adi_ad9082_adc_nyquist_zone_set(&ad9082_dev,
    					AD9082_ADC_ALL, AD9082_ADC_NYQUIST_ZONE_EVEN), err
    					!= API_CMS_ERROR_OK)
    				return err;
    			break;
    		default:
    			break;
    		}
    
    		/* Configure Synchronization Options as per Application Use-case*/
    		/* By Default Application uses Subclass 0 and Internal Sysref Synchronization*/
    		/* Note 21/26/27 Are examples of Subclass 1*/
    		switch (uc)
    		{
    		case 0: /*NCO Test Mode- No JESD*/
    			break;
    		case 26: /*ADC Test Test Mode*/
    			printf("APP: JESD RX Syncrhonization Mode: %s\r\n",
    					((jrx_param[uc].jesd_subclass == JESD_SUBCLASS_1) ?
    							"JESD_SUBCLASS_1" : "JESD_SUBCLASS_0"));
    			if (err = adi_ad9082_adc_nco_master_slave_sync(&ad9082_dev, 1, 2, 0,
    					1), err != API_CMS_ERROR_OK) /*mcs: master*/
    				return err;
    			break;
    		case 27: /*ADC Test Test Mode*/
    			printf("APP: JESD RX Syncrhonization Mode: %s\r\n",
    					((jrx_param[uc].jesd_subclass == JESD_SUBCLASS_1) ?
    							"JESD_SUBCLASS_1" : "JESD_SUBCLASS_0"));
    			if (err = adi_ad9082_adc_nco_master_slave_sync(&ad9082_dev, 0, 2, 0,
    					1), err != API_CMS_ERROR_OK) /*mcs slave*/
    				return err;
    			break;
    		default:
    			printf("APP: JESD RX Syncrhonization Mode: %s\r\n",
    					((jrx_param[uc].jesd_subclass == JESD_SUBCLASS_1) ?
    							"JESD_SUBCLASS_1" : "JESD_SUBCLASS_0"));
    			if (err = adi_ad9082_jesd_sysref_enable_set(&ad9082_dev,
    					jrx_param[uc].jesd_subclass > 0 ? 1 : 0), err
    					!= API_CMS_ERROR_OK) /* Configure and Enable/Disable Sysref Reciever*/
    				return err;
    			if (err = adi_ad9082_jesd_oneshot_sync(&ad9082_dev, 0), err
    					!= API_CMS_ERROR_OK)
    			{
    				if (err == API_CMS_ERROR_JESD_SYNC_NOT_DONE)
    				{
    					printf("APP: JESD Oneshot Synchronization Not Completed");
    				}
    				return err;
    			}
    			break;
    		}
    	}
    	/* SYSTEM Link Bring Up Sequenece
    	 *  Check AD9082 JESD PLL Lock Status
    	 *  Enable AD9082 JESD Rx/ JESD TX Links
    	 *  Ensure FPGA JESD RX/ JESD TX Links are configured
    	 *  Ensure FPGA is transmitting Data
    	 *  Toggle AD9082 JESD RX Links Enable
    	 *  Run AD9082 JESD RX 204C Calibration if Lane Rate is above Threshold AD9082_JESDRX_204C_CAL_THRESH
    	 *  Toggle AD9082 JESD RX Links Enable
    	 *  Check Link Status after short period time
    	 */
    	if (uc > 0)
    	{
    		/* Check JESD PLL LOCK Status */
    		uint8_t uc_jesd_pll_status = 0x00;
    		err = adi_ad9082_jesd_pll_lock_status_get(&ad9082_dev,
    				&uc_jesd_pll_status);
    		printf("APP: ad9082 JESD PLL lock Status: %s : %s\r\n",
    				(uc_jesd_pll_status ? "LOCKED" : "NOT LOCKED"),
    				(uc_jesd_pll_status ? "Enabling Links" : "Exiting"));
    		if (err != API_CMS_ERROR_OK)
    		{
    			return err;
    		}
    
    #if !defined(AD9177_ID)
    		/* enable ad9082 Rx Path: JESD Tx Link links */
    		switch (uc)
    		{
    		case 17:
    		case 28:
    			/*TX ONLY MODES*/
    			break;
    		default:
    			if (err = adi_ad9082_jesd_tx_link_enable_set(&ad9082_dev,
    					(jtx_param[uc][0].jesd_duallink > 0) ?
    							AD9082_LINK_ALL : AD9082_LINK_0, 1), err
    					!= API_CMS_ERROR_OK)
    				return err;
    			break;
    		}
    #endif
    #if !defined(AD9207_ID) && !defined(AD9209_ID)
    		/* enable ad9082 Tx Path: JESD Rx Link links */
    		switch (uc)
    		{
    		case 18:
    		case 29:
    		case 32:
    			/*RX ONLY MODES*/
    			break;
    		default:
    			if (err = adi_ad9082_jesd_rx_link_enable_set(&ad9082_dev,
    					(jrx_param[uc].jesd_duallink > 0) ?
    							AD9082_LINK_ALL : AD9082_LINK_0, 1), err
    					!= API_CMS_ERROR_OK)
    				return err;
    			break;
    		}
    #endif
    
    		/*Enable FPGA JESD RxTx/ Initiate Playback */
    		if (err = adi_ads9_reg_set(0x106, 0x000), err != API_CMS_ERROR_OK) /* skip_rx_link_init = 0 */
    			return err;
    		if (err = adi_ads9_reg_set(0x947, 2), err != API_CMS_ERROR_OK) /* bidir_start = 1 */
    			return err;
    		usleep(100000);
    //		if (err = ads9_wait_us(NULL, 100000), err != API_CMS_ERROR_OK)
    //			return err;
    		if (err = adi_ads9_reg_set(0x106, 0x400), err != API_CMS_ERROR_OK) /* skip_rx_link_init = 1 */
    			return err;
    		if (err = adi_ads9_reg_set(0x537, 4), err != API_CMS_ERROR_OK) /* gt_tx_ptn_play_stop = 1 */
    			return err;
    
    #if !defined(AD9207_ID) && !defined(AD9209_ID)
    		if (err = adi_ad9082_jesd_rx_link_enable_set(&ad9082_dev,
    				AD9082_LINK_ALL, 0), err != API_CMS_ERROR_OK)
    			return err;
    #endif
    		if (err = adi_ads9_reg_set(0x537, 1), err != API_CMS_ERROR_OK) /* gt_tx_ptn_play_start = 1 */
    			return err;
    #if !defined(AD9207_ID) && !defined(AD9209_ID) 
    		if (err = adi_ad9082_jesd_rx_link_enable_set(&ad9082_dev,
    				(jrx_param[uc].jesd_duallink > 0) ?
    						AD9082_LINK_ALL : AD9082_LINK_0, 1), err
    				!= API_CMS_ERROR_OK)
    			return err;
    #endif
    
    		/* calibrate jrx when lane rate is high for 204c */
    		printf("APP: Run JESD RX 204C Calibration & Enable TX Path Links\r\n");
    #if !defined(AD9207_ID) && !defined(AD9209_ID) 
    		if ((jrx_param[uc].jesd_l > 0) && (jrx_param[uc].jesd_jesdv == 2)
    				&& ((clk_hz[uc][1] * 66) > AD9082_JESDRX_204C_CAL_THRESH))
    		{
    			if (err = adi_ad9082_jesd_rx_calibrate_204c(&ad9082_dev, 1, 0x00,
    					1), err != API_CMS_ERROR_OK)
    			{
    				printf("APP: ad9082 JESD RX Calibration Error\r\n");
    				return err;
    			}
    			if (err = adi_ad9082_jesd_rx_link_enable_set(&ad9082_dev,
    					AD9082_LINK_ALL, 0), err != API_CMS_ERROR_OK)
    				return err;
    			if (err = adi_ad9082_jesd_rx_link_enable_set(&ad9082_dev,
    					(jrx_param[uc].jesd_duallink > 0) ?
    							AD9082_LINK_ALL : AD9082_LINK_0, 1), err
    					!= API_CMS_ERROR_OK)
    				return err;
    			if (err = adi_ad9082_jesd_rx_link_enable_set(&ad9082_dev,
    					AD9082_LINK_ALL, 0), err != API_CMS_ERROR_OK)
    				return err;
    			if (err = adi_ad9082_jesd_rx_link_enable_set(&ad9082_dev,
    					(jrx_param[uc].jesd_duallink > 0) ?
    							AD9082_LINK_ALL : AD9082_LINK_0, 1), err
    					!= API_CMS_ERROR_OK)
    				return err;
    		}
    #endif
    		/* delay some time for link to be stable */
    		usleep(100000);
    //		if (err = ads9_wait_us(NULL, 10000000), err != API_CMS_ERROR_OK)
    //			return err;
    		/* check link status */
    		if (err = app_show_link_status(&ad9082_dev), err != API_CMS_ERROR_OK)
    			return err;
    	}
    
    	{ /* free resource and close platform */
    		/* free user data */
    //		if (err = ads9_user_data_free(&ad9082_dev.hal_info.user_data), err
    //				!= API_CMS_ERROR_OK)
    //			return err;
    //		if (err = ads9_user_data_free(&hmc7044_dev.hal_info.user_data), err
    //				!= API_CMS_ERROR_OK)
    //			return err;
    		/* close platform */
    //		if (err = ads9_hw_close(), err != API_CMS_ERROR_OK)
    //			return err;
    	}
    
    	printf("\r\n");
    	return API_CMS_ERROR_OK;
    }
    
    int32_t app_show_link_status(adi_ad9082_device_t *device)
    {
    	int32_t err;
    	uint32_t fpga_use_204c;
    	uint32_t fpga_jrx_np, fpga_jtx_np;
    
    	/* get link configuration */
    	if (err = adi_ads9_reg_get(0x943, &fpga_use_204c), err != API_CMS_ERROR_OK)
    		return err;
    	printf("APP: Checking JESD link status: %s Mode \r\n",
    			(fpga_use_204c ? "204C" : "204B"));
    
    	if (err = adi_ads9_reg_get(0x121, &fpga_jrx_np), err != API_CMS_ERROR_OK)
    		return err;
    	if (err = adi_ads9_reg_get(0x521, &fpga_jtx_np), err != API_CMS_ERROR_OK)
    		return err;
    
    #if !defined(AD9207_ID) && !defined(AD9209_ID)
    	/* get link status of tx */
    	uint16_t ad9082_jrx_link_status[2];
    	uint32_t fpga_jesd204b_tx_status;
    	uint8_t ad9082_jrx_tpl_link_status[2];
    	if (err = adi_ads9_reg_get(0x54e, &fpga_jesd204b_tx_status), err
    			!= API_CMS_ERROR_OK)
    		return err;
    	if ((fpga_jtx_np & 0x00ff) > 0)
    	{ /* link0 */
    		if (err = adi_ad9082_jesd_rx_link_status_get(device, AD9082_LINK_0,
    				&ad9082_jrx_link_status[0]), err != API_CMS_ERROR_OK)
    			return err;
    	}
    	if ((fpga_jtx_np & 0xff00) > 0)
    	{ /* link1 */
    		if (err = adi_ad9082_jesd_rx_link_status_get(device, AD9082_LINK_1,
    				&ad9082_jrx_link_status[1]), err != API_CMS_ERROR_OK)
    			return err;
    	}
    	err = adi_ad9082_jesd_rx_link_select_set(device, AD9082_LINK_0);
    	err = adi_ad9082_device_spi_register_get(device, 0x04a0,
    			&ad9082_jrx_tpl_link_status[0]);
    	err = adi_ad9082_jesd_rx_link_select_set(device, AD9082_LINK_1);
    	err = adi_ad9082_device_spi_register_get(device, 0x04a0,
    			&ad9082_jrx_tpl_link_status[1]);
    
    	if (fpga_use_204c == 0)
    	{
    		if ((fpga_jtx_np & 0x00ff) > 0)
    		{ /* link0 */
    			printf(
    					((ad9082_jrx_link_status[0] & 0x00f) == 0x00f) ?
    							"  AD9082 JRX link0 is up." :
    							"  AD9082 JRX link0 isn't up.");
    			printf(
    					"AD9082 JRX Status = 0x%.4x, AD9082 JRX TPL Status =0x%.2x FPGA JTX Status = 0x%.2x\r\n",
    					ad9082_jrx_link_status[0], ad9082_jrx_tpl_link_status[0],
    					fpga_jesd204b_tx_status);
    		}
    		if ((fpga_jtx_np & 0xff00) > 0)
    		{ /* link1 */
    			printf(
    					((ad9082_jrx_link_status[1] & 0x00f) == 0x00f) ?
    							"  AD9082 JRX link1 is up." :
    							"  AD9082 JRX link1 isn't up.");
    			printf(
    					"AD9082 JRX Status = 0x%.4x, AD9082 TPL Status =0x%.2x, FPGA JTX Status = 0x%.2x\r\n",
    					ad9082_jrx_link_status[1], ad9082_jrx_tpl_link_status[1],
    					fpga_jesd204b_tx_status);
    		}
    	}
    	else
    	{ /* 204C */
    		if ((fpga_jtx_np & 0x00ff) > 0)
    		{ /* link0 */
    			printf(
    					((ad9082_jrx_link_status[0] & 0xf00) == 0x600) ?
    							"  AD9082 JRX link0 is up." :
    							"  AD9082 JRX link0 isn't up.");
    			printf(
    					"AD9082 JRX Status = 0x%.4x, AD9082 TPL Status =0x%.2x, FPGA JTX Status = 0x%.2x\r\n",
    					ad9082_jrx_link_status[0], ad9082_jrx_tpl_link_status[0],
    					fpga_jesd204b_tx_status);
    		}
    		if ((fpga_jtx_np & 0xff00) > 0)
    		{ /* link1 */
    			printf(
    					((ad9082_jrx_link_status[1] & 0xf00) == 0x600) ?
    							"  AD9082 JRX link1 is up." :
    							"  AD9082 JRX link1 isn't up.");
    			printf(
    					"AD9082 JRX Status = 0x%.4x, AD9082 TPL Status =0x%.2x, FPGA JTX Status = 0x%.2x\r\n",
    					ad9082_jrx_link_status[1], ad9082_jrx_tpl_link_status[1],
    					fpga_jesd204b_tx_status);
    		}
    	}
    #endif
    
    #if !defined(AD9177_ID)
    	/* get link status of rx */
    	uint16_t ad9082_jtx_link_status[2];
    	uint32_t fpga_jesd204b_rx_status, fpga_jesd240c_rx_status,
    			fpga_jesd204c_link_err_cnt, fpga_rx_err_total_cnt;
    	if (err = adi_ads9_reg_get(0x14e, &fpga_jesd204b_rx_status), err
    			!= API_CMS_ERROR_OK)
    		return err;
    	if (err = adi_ads9_reg_get(0x205, &fpga_jesd240c_rx_status), err
    			!= API_CMS_ERROR_OK)
    		return err;
    	if (err = adi_ads9_reg_get(0x160, &fpga_rx_err_total_cnt), err
    			!= API_CMS_ERROR_OK)
    		return err;
    	if (err = adi_ads9_reg_get(0x220, &fpga_jesd204c_link_err_cnt), err
    			!= API_CMS_ERROR_OK)
    		return err;
    	if ((fpga_jrx_np & 0x00ff) > 0)
    	{ /* link0 */
    		if (err = adi_ad9082_jesd_tx_link_status_get(device, AD9082_LINK_0,
    				&ad9082_jtx_link_status[0]), err != API_CMS_ERROR_OK)
    			return err;
    	}
    	if ((fpga_jrx_np & 0xff00) > 0)
    	{ /* link1 */
    		if (err = adi_ad9082_jesd_tx_link_status_get(device, AD9082_LINK_1,
    				&ad9082_jtx_link_status[1]), err != API_CMS_ERROR_OK)
    			return err;
    	}
    	if (fpga_use_204c == 0)
    	{
    		if ((fpga_jrx_np & 0x00ff) > 0)
    		{ /* link0 */
    			printf(
    					(((ad9082_jtx_link_status[0] & 0xff) == 0x7d)
    							&& ((fpga_jesd204b_rx_status & 0x10) == 0x00)) ?
    							"  AD9082 JTX link0 is up." :
    							"  AD9082 JTX link0 isn't up.");
    			printf(
    					"AD9082 JTX Status = 0x%.4x, FPGA JRX Status = (0x%.2x, 0x%.2x), EMB_ERR_CNT = %d, CRC_ERR_CNT = %d, RX_ERR_CNT = %d\r\n",
    					ad9082_jtx_link_status[0], fpga_jesd204b_rx_status,
    					fpga_jesd240c_rx_status, fpga_jesd204c_link_err_cnt >> 16,
    					fpga_jesd204c_link_err_cnt & 0xffff, fpga_rx_err_total_cnt);
    		}
    		if ((fpga_jrx_np & 0xff00) > 0)
    		{ /* link1 */
    			printf(
    					(((ad9082_jtx_link_status[1] & 0xff) == 0x7d)
    							&& ((fpga_jesd204b_rx_status & 0x10) == 0x00)) ?
    							"  AD9082 JTX link1 is up." :
    							"  AD9082 JTX link1 isn't up.");
    			printf(
    					"AD9082 JTX Status = 0x%.4x, FPGA JRX Status = (0x%.2x, 0x%.2x), EMB_ERR_CNT = %d, CRC_ERR_CNT = %d, RX_ERR_CNT = %d\r\n",
    					ad9082_jtx_link_status[1], fpga_jesd204b_rx_status,
    					fpga_jesd240c_rx_status, fpga_jesd204c_link_err_cnt >> 16,
    					fpga_jesd204c_link_err_cnt & 0xffff, fpga_rx_err_total_cnt);
    		}
    	}
    	else
    	{ /* 204C */
    		if ((fpga_jrx_np & 0x00ff) > 0)
    		{ /* link0 */
    			printf(
    					(((ad9082_jtx_link_status[0] & 0x60) == 0x60)
    							&& ((fpga_jesd204b_rx_status & 0x10) == 0x00)) ?
    							"  AD9082 JTX link0 is up." :
    							"  AD9082 JTX link0 isn't up.");
    			printf(
    					"AD9082 JTX Status = 0x%.4x, FPGA JRX Status = (0x%.2x, 0x%.2x), EMB_ERR_CNT = %d, CRC_ERR_CNT = %d, RX_ERR_CNT = %d\r\n",
    					ad9082_jtx_link_status[0], fpga_jesd204b_rx_status,
    					fpga_jesd240c_rx_status, fpga_jesd204c_link_err_cnt >> 16,
    					fpga_jesd204c_link_err_cnt & 0xffff, fpga_rx_err_total_cnt);
    		}
    		if ((fpga_jrx_np & 0xff00) > 0)
    		{ /* link1 */
    			printf(
    					(((ad9082_jtx_link_status[1] & 0x60) == 0x60)
    							&& ((fpga_jesd204b_rx_status & 0x10) == 0x00)) ?
    							"  AD9082 JTX link1 is up." :
    							"  AD9082 JTX link1 isn't up.");
    			printf(
    					"AD9082 JTX Status = 0x%.4x, FPGA JRX Status = (0x%.2x, 0x%.2x), EMB_ERR_CNT = %d, CRC_ERR_CNT = %d, RX_ERR_CNT = %d\r\n",
    					ad9082_jtx_link_status[1], fpga_jesd204b_rx_status,
    					fpga_jesd240c_rx_status, fpga_jesd204c_link_err_cnt >> 16,
    					fpga_jesd204c_link_err_cnt & 0xffff, fpga_rx_err_total_cnt);
    		}
    	}
    #endif
    
    	return API_CMS_ERROR_OK;
    }

  • Hi,

    The error device_boot_pre_clock function comes from clock configuration error. Since you are using the HMC7044, it could mean that the HMC7044 is not configured correctly. I also saw that you are experiencing multiple SPI issues, especially on the HMC7044 side. Could you please verify that the HAL code is pointing to the HMC7044 device correctly when executing SPI writes/reads to/from the HMC7044?

    Judy

  • Hi  

    The function adi_ad9082_device_boot_pre_clock takes argument of device handler of ADC but not of HMC.

    Also, in LOG_B.txt at line 126 it shows "APP: Reference Clocks Configured" showing that PLL is locked, else it would have show "HMC7044: PLL is not locked".


    The SPI calls which are observed to be failing are related to registers which are not explained in UG-1578. I have checked HAL of both ADC and HMC and they appear to work as expected. The HMC registers are read back after every write at HAL layer to confirm the write operation.

    125MHz with 50mV clock signal was observed on SYSREF_P on ADC9082 add on card

    which confirms the configuration of HMC.

    The issue is long pending.

    As per suggestion from Analog Devices, we have integrated API to our code and running it on Evaluation board. The  API calls fail to execute at access (read/write) for specific registers which are not  explained in UG-1578. We are now stuck in a state where we cannot figure out why the calls are failing as technical literature to those registers is not provided in UG-1578 nor in API. The purpose of these registers is also not clear.

    kindly, request to assist in configuring of AD9082.