Post Go back to editing

JESD204C Lane not getting up

Category: Software
Product Number: VCU118 + AD9082 Eval Board
Software Version: StandAlone

I am using VCU118 board + AD9082 with setup as shown in link https://wiki.analog.com/resources/eval/user-guides/ad9081_fmca_ebz/quickstart/microblaze but with AD9082 board.

Using HMC to generate 125 MHz as CLK and Feeding 4.4GHz (5dBm) to EXT_CLK input of AD9082 and bypassing the PLL, capacitors C4D & C6D are mounted and C3D and C5D are un-mounted.

I am able to read and write into ADC9082 & HMC registers.

The aim is to energize the ADC of AD9082 @ 4.4GHz, and transmit the sampled data over JESD204C 64b/66b.

In order to do so, The following registers are configured as per UG-1578.


SNO ADDR DESC B7 B6 B5 B4 B3 B2 B1 B0 VAL DESC
1 0x001A JTX_PAGE 0 0 0 0 0 0 0 1 0x01 EN LINK 0 ONLY
2 0x0710 FORCE_LINK_RESET_REG 0 0 0 1 0 0 0 1 0x11 FORCE RESET SELECTED JTX LINK
3 0x0600 JTX_CORE_0_CONV0 0 0 0 0 0 0 0 0 0x00
4 0x0601 JTX_CORE_0_CONV1 0 0 0 0 0 0 0 1 0x01
5 0x0750 PWR_DN 0 0 0 0 0 0 0 0 0x00 POWER UP Serializer
6 0xEFFF DELAY 0 0 0 0 0 0 0 0 0x00 DELAY
7 0x061B JTX_CORE2_LANE0 0 0 0 0 0 0 0 0 0x00 FORCE DOWN LANE 0
8 0x061C JTX_CORE2_LANE1 0 0 0 0 0 0 0 1 0x01 FORCE DOWN LANE 1
9 0x061D JTX_CORE2_LANE2 0 0 0 0 0 0 1 0 0x02 FORCE DOWN LANE 2
10 0x061E JTX_CORE2_LANE3 0 0 0 0 0 0 1 1 0x03 FORCE DOWN LANE 3
11 0x061F JTX_CORE2_LANE4 0 0 0 0 0 1 0 0 0x04 FORCE DOWN LANE 4
12 0x0620 JTX_CORE2_LANE5 0 0 0 0 0 1 0 1 0x05 FORCE DOWN LANE 5
13 0x0621 JTX_CORE2_LANE6 0 0 0 0 0 1 1 0 0x06 FORCE DOWN LANE 6
14 0x0622 JTX_CORE2_LANE7 0 0 0 0 0 1 1 1 0x07 FORCE DOWN LANE 7
15 0xEFFF DELAY 0 0 0 0 0 0 0 0 0x00 DELAY
16 0x0782 EN_DRVSLICEOFFSET 0 0 0 0 1 1 1 1 0x0F EN_DRVSLICEOFFSET
17 0x0752 JTX_SWING 0 0 0 1 0 0 0 1 0x11 0.85*SVDD1, Default
18 0x0763 PRE_TAP_LEVEL_CH0 0 0 0 0 0 0 0 0 0x00 0dB, default
19 0x075A POST_TAP_LEVEL1 0 0 0 0 0 0 0 0 0x00 0dB, default
20 0x0789 MAIN_DATA_INV 0 0 0 0 0 0 0 0 0x00 JTX Invert = normal, default
21 0x0773 RSTB 1 1 1 1 1 1 1 1 0xFF Reset Digital Logic
22 0xEFFF DELAY 0 0 0 0 0 0 0 0 0x00 DELAY
23 0x0773 RSTB 0 0 0 0 0 0 0 0 0x00 Reset Digital Logic
24 0xEFFF DELAY 0 0 0 0 0 0 0 0 0x00 DELAY
25 0x0773 RSTB 1 1 1 1 1 1 1 1 0xFF Reset Digital Logic
26 0xEFFF DELAY 0 0 0 0 0 0 0 0 0x00 DELAY
27 0x0710 FORCE_LINK_RESET_REG 0 0 0 1 0 0 0 1 0x11 FORCE RESET SELECTED JTX LINK
28 0x001A JTX_PAGE 0 0 0 0 0 0 0 1 0x01 EN LINK 0 ONLY
29 0x0721 PLL_ENABLE_CTRL 0 0 1 0 0 0 0 0 0x20 LCPLL_JTX_PLL_BYPASS_LOCK

30 0x0712 K_EMB_QC_OVERRIDE 0 0 0 0 0 0 0 1 0x01 k_emb qc values override in qc mode
31 0x063D JTX_L0_3 1 0 0 0 0 1 1 1 0x87 Scramble En
32 0x063E JTX_F_CFG 0 0 0 0 0 0 0 0 0x00 1 Octate
33 0x063F JTX_K_CFG 1 1 1 1 1 1 1 1 0xFF K=256
34 0x0640 JTX_M_CFG 0 0 0 0 0 0 0 1 0x01 M= 2
35 0x0641 JTX_CS_CFG 0 0 0 0 1 1 1 1 0x0F Default, no Of CS = 0, 16 bit resolution
36 0x0642 JTX_SUBCLASSV_CFG 0 0 1 0 1 0 1 1 0x2B Sub-Class 1, ADC 12 bits per sample
37 0x0643 JTX_JESDV_CFG 0 0 0 0 0 0 0 1 0x01 S = no of samples per frame per cycle = 1
38 0x0636 JTX_TPL_6 0 0 0 0 0 0 0 0 0x00 MASK for sub-Class 1
39 0x0644 JTX_HD_CFG 1 0 0 0 0 0 0 0 0x80 HD bit
40 0x0773 RSTB 1 1 1 1 1 1 1 1 0xFF Reset Digital Logic
41 0xEFFF DELAY 0 0 0 0 0 0 0 0 0x00 DELAY
42 0x0773 RSTB 0 0 0 0 0 0 0 0 0x00 Reset Digital Logic
43 0xEFFF DELAY 0 0 0 0 0 0 0 0 0x00 DELAY
44 0x0773 RSTB 1 1 1 1 1 1 1 1 0xFF Reset Digital Logic
45 0xEFFF DELAY 0 0 0 0 0 0 0 0 0x00 DELAY
46 0x0773 RSTB 1 1 1 1 1 1 1 1 0xFF
47 0x0668 JTX_DL_204C_1 0 0 0 0 0 0 0 0 0x00 Default
48 0x0611 JTX_CORE_1 0 0 0 1 0 0 0 0 0x10
49 0x062E JTX_CORE_13 0 0 0 0 0 0 0 1 0x01
50 0x0670 JTX_PHY_IFX_0_LANEn 0 0 0 0 0 0 0 0 0x00
51 0x0671 JTX_PHY_IFX_1_LANEn 0 0 0 0 0 0 0 0 0x00
52 0x0672 JTX_PHY_IFX_2_LANEn 0 0 0 0 0 0 0 0 0x00 Async False
53 0x0673 JTX_PHY_IFX_3_LANEn 0 0 0 0 0 0 0 0 0x00 Async Mode
54 0x0674 JTX_PHY_IFX_4_LANEn 0 0 0 0 0 0 0 0 0x00 Selects JESD204B/C
parallel data processing width. 0 = 66 bits
(204C)
55 0x0675 JTX_PHY_IFX_5_LANEn 0 0 0 0 0 0 0 0 0x00
56 0x0676 JTX_PHY_IFX_6_LANEn 0 0 0 0 0 0 0 0 0x00
57 0x0677 JTX_PHY_IFX_7_LANEn 0 0 0 0 0 0 0 0 0x00

58 0x0630 JTX_TPL_0 0 0 0 0 0 0 0 0 0x00
59 0x070A JTX_SER_BIT_FIELD 0 0 0 0 0 0 0 1 0x01 Lane rate > 16Gbps, may be checked
60 0x0762 PARDATAMODE_SER 0 0 0 0 0 0 0 0 0x00 FORCE RESET SELECTED JTX LINK
61 0x0797 SYNCA_CTRL 0 0 0 0 1 0 0 1 0x09 One shot sync
62 0x0798 SYNCB_CTRL 0 0 0 0 1 0 0 1 0x09
63 0x0706 JTX_SER_CLK_INVERT 0 0 0 0 0 0 0 0 0x00
64 0x0727 LCPLL_REF_CLK_DIV1_REG 0 0 0 1 0 0 0 1 0x11
65 0x0717 DVM_LCPLL_RC_RX 0 0 0 0 0 0 1 0 0x02
66 0x0710 FORCE_LINK_RESET_REG 0 0 0 1 0 0 0 1 0x11
67 0x00B8 SYSREF_MODE 0 0 0 0 0 0 1 0 0x02

During setting it is observed that when setting reg 0x061B to 0x0622 the value read back is 0x80, 0x81...0x87 not 0x00, 0x01, .... 0x07.

which implies that the Lane is not up. JTX_LANE0_PD_STATUS bit 7 is high, implying Lane is power down. Requested to provide possible reason Lane is not UP and also share the correct setting to be carried out.

 

The following values are shared for device info:

REG DATA
0x701                  0x80
0x722                  0x1
0x713                  0x0
0x0                    0x18
0x3                    0xF
0x4                    0x82
0x5       0x90
0x6     0x23
0xB     0x1
0xC     0x56
0xD     0x4
0x10     0x0
0x11     0x0
0x12     0x0
0x13     0x0
0x210     0x3F
0x211     0xF
0x212     0x3F
0x213     0x3F
0x2107                 0x0
0x2108                 0x0
0x210B                 0x0
0x210C                 0x0

It is also observed that the temperature registers 0x2107, 0x2108, 0x210B & 0x210C are read as zeros.

  • Hello,

    With regard to description "Using HMC to generate 125 MHz as CLK and Feeding 4.4GHz (5dBm) to EXT_CLK input of AD9082 and bypassing the PLL, capacitors C4D & C6D are mounted and C3D and C5D are un-mounted"............................it would appear that the "SERDES REFCLK" is either not being provided and/or is not locked to the 4.4 GHz external clock signal.   For a successful JESD204 link to occur.............both the clock provided to the AD9082  (i.e. EXT_CLK in your case) as well as the reference clock provided to FPGA (which is used by its SERDES PLL) must be phase locked to ensure that the lane rates are at exactly the same frequency and are phase aligned (i.e. no drift in phase).   Note that when one uses the HMC7044 to provide both the clock to the AD9082 as well as the ref clock (via FMC connector pins).................these two signals being derived off the same HMC PLL2/VCO are considered locked.

    With regard to your settings...................the SPI writes that occur should be based on the AD9082  API which generates all the necessary SPI writes to configure the device (as well as exact order in which they must occur).  It is unclear from your description on whether the AD9082 SPI configuration file is based on our API.  

    Note that our ACE based GUI provides a means of configuring the AD9082 from a high level when interfacing to our ADS9-V2 FPGA capture board.  One can inspect the "SPI writes" used to configure the device via downloading the log file.  Assuming that you have a ADS9-V2 board..............perhaps it would be best to use this 1st to verify that your desired configuration does work before moving to implement on another FPGA platform.  Note that the Tx (and Rx) ref clock corresponds to the clock frequency that is required by the FPGA to that its clocks are phase aligned with the AD9082.  In the case of applying an external ref clock to the AD9082 FMCA EVB...............one must also apply an external reference clock to the FPGA via another RF generator that is phase locked (via 10 MHz REF OUT/IN connection on back of instrument with master/slave relationship).

    Regards



  • Hello,

    I will let my software colleagues who support the example code associated with VCU118.  The earlier point about using ext clock is still relevant.   As such............I suggest that you use HMC7044 as your clocking solution (C5D, C3D populated) and try one of the proven design examples to demonstrate that you have working software and set-up.  Once this has been demonstrated...........then create your own use case example (still using the HMC7044 as clock source) and start debug process.

    Regards




  • Thank you for the reply,

    1) I will try phase locking both the clocks and check if lane gets up.

    2) I have tried running the hardware with the highlighted files, as per procedure of https://wiki.analog.com/resources/eval/user-guides/ad9081_fmca_ebz/quickstart/microblaze

    It is observed that for my AD9082 daughter board when it boots, in "dmesg" it said "ad9082 spi0.0: Unrecognized CHIP_ID 0x9082"

    I think those files are compiled for only AD9081 but not for AD9082,

    When booting through those files, IIO scope shows only HMC but not AD9082.

    If possible please share compiled binaries for AD9082 with VCU118.

    3) I don't have ADS9-V2 FPGA capture board at present and ACE software doesn't update its memory map. I have raised a support request for the same in https://ez.analog.com/wide-band-rf-transceivers/mixed-signal-front-ends-mxfe/f/q-a/558109/memory-map-not-updating-after-clicking-apply-of-quick-configuration-no-harware.

    4) It is also observed that the temperature registers 0x2107, 0x2108, 0x210B & 0x210C are read as zeros, possible reasons for such behavior.

    The only thing possible to test for me in current setup is with option 1, I shall try it and get back.

    Regards,

    Faiz Ahmed.