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AD9207 ADC Test Mode ramp - expected data in decimate by 4 mode


I have enabled the ADC datapath test mode, to output a ramp on both the I and Q channels.

My application is running the each ADC at 6Gsps Real, decimated by 4 to give 1.5Gsps IQ and sent out over 4 JESD204C links.   (L=4, F=8, M=2, S=8, HD=0, K=32, N=16, NP=16, SCR=1, Dual Link=1, V=2 , Mode=13, ModeS=3, CSR=0, SC=0). The lane rate is 12.375Gbits/s.   I am using one CDDC and one FDDC.

I am seeing the following output on both I and Q for the "ramp":

0,1,4,5,8,9,12,13,16,17,20,21 etc.  Each number is a 16bit sample.  As you can see I am missing ever other pair of samples.

Is this the expected ramp output in this configuration?  

If I enable the ramp test on the jesd_tx instead (jesd_tx_ramp_test) then I receive the same ramp on each of the 4 lanes, with no missing counts, so I think the JESD204C link is working as expected. 

At the moment, when I capture an RF signal the spectrum is dreadful and looks very much like I'm missing samples...

Thanks for the help.

Added note about the RF signal spectrum looking poor.
[edited by: daedalus at 7:37 PM (GMT -5) on 10 Feb 2022]
  • Hi,

    I didnt have a AD9082 at my disposal, but i used the AD9081-FMCA-EBZ in this setup

    I then used the acemacro to send the commands to enable test mode as ramp

    -- Analog Devices, Inc. evaluation macro file
    ## Copyright (c) 2019 Analog Devices, Inc. All Rights Reserved. This software is proprietary to Analog Devices, ##Inc. and its licensors.
    ## These code snippets are provided ‘as is’ with no warranties, guarantees of suitability, or acceptance of any ## ## liability, for their use.
    @Subsystem_1.AD9081-FMCA-EBZ.AD9081: Evaluation.Control.RawReadRegister(0x18);
    > @Subsystem_1.AD9081-FMCA-EBZ.AD9081.AD9081 Memory Map: @SpiWriteRead(); [skip]
    @Subsystem_1.AD9081-FMCA-EBZ.AD9081: Evaluation.Control.RawWriteRegister(0x18, 0x0FF);
    > @Subsystem_1.AD9081-FMCA-EBZ.AD9081.AD9081 Memory Map: @SpiWriteRead(); [skip]
    @Subsystem_1.AD9081-FMCA-EBZ.AD9081: Evaluation.Control.RawWriteRegister(0x0624, 0x08);
    @Subsystem_1.AD9081-FMCA-EBZ.AD9081: @ReadSettings(); [skip]

    you can copy this into a txt file and save it as <your_filename>.acemacro and run it in ACE. you may have to change the board ID to AD9082-FMCA-EBZ. I do see a ramp in the display

    inspecting the raw data, i am also able to see that the data decrements/increments by 1 on all eight virtual converters (since M = 8 in my setup)

  • Thanks for the help Umesh.  Was really useful in finding an error in my own firmware.  I'm getting the correct ramp now.

  •  , that is amazing. Thank you for letting me know. Good Luck with your design.