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AD9082 about ADC CLOCK GENERATION Control



		

			

									
						jinyoung
					
							

			
				
									
											
							 		
		        	            							
			
			    	
			                    
                
				                on Jan 4, 2022 
				
			
			
		


				
		

		    		    
		    
		    	
			
DEARS.


I have a question about AD9082.


 ad9082


1. Is it possible to set all SUB-ADC 1,2,3,4 ADC CLOCK the same?


2. If possible, how do you set it up? (API or REG)




---- TEST AD9082 SETTING-------
ADC1 PORT --> SUB ADC1(NCO:3G)    -> FPGA(LOOPBACK) -> SUB DAC1(NCO:3G)    --> DAC1(NCO:3.75G) -> DAC1 PORT
                     |-> SUB ADC2(NCO:3.5G) -> FPGA(LOOPBACK) -> SUB DAC2(NCO:3.5G)  -|
                     |-> SUB ADC3(NCO:4G)    -> FPGA(LOOPBACK) -> SUB DAC3(NCO:4G)     -|
                     |-> SUB ADC4(NCO:4.5G) -> FPGA(LOOPBACK) -> SUB DAC4(NCO:4.5G)  -|


 






Thank you.