CGS. ILAS errors while setting up the AD9082 in full bandwidth mode using external clocking

Hi, have you modified the board to allow for the external clock? figures 18, 19 and 20 of UG-1829

Have you also verified the instrumentation? figure 30 of UG-1829

Hi, Thanks for your response. We have done all that. Our board is the ad9082 so the setup for the external clock looks like that of fig. 18 of UG-1829. That is how we were able to provide the 6GHz clock from the signal generator to the ad9082 board. 

We also provided a 750Mhz signal from another signal generator to the ADS9-V2EBZ FPGA board. We also synced the signal generators (together with a spectrum analyzer) by means of a 10MHz sync as described in UG-1829

Hello UmeshJ

The problem has been solved. I thought our PCB guys had already changed the capacitors upon arrival of the board, but after checking again I realized they had not. They changed it and now I am able to program the board successfully with the external clock input. So, you pointed us in the right direction. Thanks. 

A few more question though;

1. At certain times, after loading a session that worked well (Rx link, Tx Link both on, Data captured successfully) programming the chip fails with Tx, Rx CGS error and Rx ILAS error, and then I'll have to try a couple more times before it works again. Is there something thats causing this? I ask because we are going to migrate the settings to our custom board and hence I want to know if there is something that needs to be checked when the chip suddenly decides not to come up.

2. After programming the chip, I see that the JESD204 PLL Lock (Low) lights up. However, the Links are brought up and Data capture is possible

Hello AlexAntwi, I am glad you were able to get the eval board working properly after the appropriate board modification. 

1. This may be an ACE issue. there is nothing in the AD9082 device that will result in this behaviour. Can you please make sure you are running the latest versions of ACE and the plugin? I have had this happen in the past, and the only way to recover was power cycle the ADS9-v2 and restart the ACE software. But, after the recent updates to ACE and the plugin, I havent seen this happen. One thing to note is, if you are changing from op-case 1 to op-case 2, you need to change the clock settings for op-case 2 done before you hit Apply in the configuration settings. 

2. the JESD204 PLL Lock (Low) is for the fpga. i believe the fpga trx has two PLLs for various line rate ranges. the ACE tool is essentially polling these registers to make sure the link is active on both sides (AD9082 and fpga). 

Okay, then I do not have to worry too much since we'll take care of the FPGA side. Thanks UmeshJ