AD9081 Low latency digital loopback mode (ADC to DAC)


The prelim datasheet of AD9081 specifies that the part supports Low latency digital loopback mode (ADC to DAC).

1) What is the latency between ADC and DAC path without decimation and interpolation filters.

2) Whether the low latency loop back mode selection is possible through pin mode. Since we are looking at application whether digital loop back is required for around 1 to 3 us (till the ADC data is received over JESD link and the decimation filters settle down). So please do let us know the control mechanism available to select between the local loop back and external DAC data.

3) Also is there a provision to scale the ADC data prior to sending to DAC for loopback.

  • 0
    •  Analog Employees 
    on Jun 18, 2019 8:48 PM


    Answers to your questions are as follows:

    1) Latency is on the order of 187 clock cycles with the clock period being determined by the ADC/DAC clock rate.

    2) Low latency loopback is set via a SPI register bit.  

    3) For direct loopback mode, no digital  gain control block is available in the datapath for rescaling.