Analog.com Analog Dialogue Wiki English
Analog.com Analog Dialogue Wiki 简体中文
EngineerZone
EngineerZone
  • Site
  • User
  • Site
  • Search
  • User
EngineerZone
EngineerZone
  • Log in
  • Site
  • Search
  • Log in
  • Home
  • Blogs ⌵
    • EngineerZone Spotlight
    • The Engineering Mind
  • Browse ⌵
    • All Groups
    • All Members
  • Support ⌵
    • 3D ToF Depth Sensing
    • Amplifiers
    • Analog Microcontrollers
    • Analysis Control Evaluation (ACE) Software
    • Audio
    • Clock and Timing
    • Data Converters
    • Design Tools and Calculators
    • Direct Digital Synthesis (DDS)
    • Embedded Vision Sensing
    • Energy Monitoring and Metering
    • FPGA Reference Designs
    • Industrial Ethernet
    • Interface and Isolation
    • Low Power RF Transceivers
    • MEMS Inertial Sensors
    • Motor Control Hardware Platforms
    • Optical Sensing
    • Power By Linear
    • Processors and DSP
    • Reference Circuits
    • RF and Microwave
    • Signal Chain Power (SCP)
    • Switches/Multiplexers
    • Temperature Sensors
    • Video
    • Wide Band RF Transceivers
    • Wireless Sensor Networks Reference Library
  • My EZ
  • More
  • Cancel
  • 主页
  • 浏览 ⌵
    • 收件箱
    • 个人设置
    • 会员
    • 专区列表
  • 论坛专区 ⌵
    • 放大器专区
    • 精密转换器专区
    • 音频专区
    • ADE电能计量专区
    • MEMS和传感器专区
    • 接口和隔离专区
    • Power 中文专区
    • ADUC微处理器专区
    • 锁相环专区
    • 开关和多路复用器专区
    • 温度传感器
    • 基准电压源专区
    • 资源库
    • 论坛使用指南
    • 技术支持参考库
    • 在线研讨会
    • 论坛社群活动
    • 论坛激励活动
  • More
  • Cancel
Design Support AD9361/AD9363/AD9364
  • Wide Band RF Transceivers
  • More
Design Support AD9361/AD9363/AD9364
Documents TDD Mode Switching Time
  • Q&A
  • Discussions
  • Documents
  • File Uploads
  • Video/Images
  • Tags
  • Managers
  • More
  • Cancel
  • New
Design Support AD9361/AD9363/AD9364 requires membership for participation - click to join
  • Documents
  • AD9361 initialization scripts
  • AD9361 Transmit Quadrature Calibration (Tx Quad Cal)
  • AD9361/4 SYNTHESIZER LOOK UP TABLE
  • AD936x Built in Self Test (BIST)
  • AD936x digital interface capacitive load drive in CMOS mode
  • AD936x documentation changes
  • AD936x Local Oscillator [LO]
  • AD936x maximum Rx digital path data rates
  • AD936x Rx ADC basic operation and output rates
  • AD936x Temperature sensor
  • AD936x_DCOFFSET_ISSUE
  • DESIGN SUPPORT COMMUNITY
  • Gain Tables in .csv format
  • General RF Front End Matching Methodology
  • GUIDELINES FOR ACCESSING TECHNICAL SUPPORT
  • Hand On Wireless Communications Seminar (Feb-Mar 2018)
  • Noise Figure vs. Gain Index Plots
  • Out-of-Band and In-Band IIP3 Measurements
  • TDD Mode Switching Time
  • Transmit Power monitor (TPM) AD936x

TDD Mode Switching Time

There are several modes in the AD9361 that can address TDD applications and it is important to pick the most effective mode for the application at hand.  The ENSM and PLL sections of the user guide describe TDD switching as well.  The ENSM guide also explains the SPI and the pin-control methods for controlling the ENSM and the LO.

Several factors affect how quickly the AD9361 can switch from Rx to Tx and vice versa including:

  • The RF VCO calibration duration which is dependent on the scaled reference clock frequency.  Higher frequencies result in faster calibration times as described in the PLL user guide.  The time is always greater than 37us.
  • RF PLL lock time of approximately 15 us, regardless of clock rates.
  • Rx and Tx flush, described in the ENSM user guide and is dependent on the ADC clock.
  • Tx DAC power up time is approximately 18us regardless of configuration and only affects switch time when moving to the Tx state.
  • Signal path latency is dependent on clock rates and filter configurations which can vary greatly.  It always must be accommodated so it not delineated in the methods below.

The Rx to Tx or Tx to Rx maximum switching time is different for each of the modes described below.  Knowing the maximum time allowed by the application helps determine the best option.

  • Standard ENSM TDD Mode: VCO calibrations occur as the ENSM moves among its states and it is not possible to enter the Rx state while the Rx PLL is unlocked.  Similarly for the Tx state and Tx PLL.  After the calibration, the PLL locks.  Tx DAC power up time (if changing to Tx) and flush time also need to take place but these can occur in parallel with the PLL switch.  Standard ENSM TDD mode is usually dominated by the VCO calibration time.
  • Standard TDD mode/No VCO cal: This option uses the TDD ENSM mode but doesn’t allow RF VCO calibrations when the ENSM switches states. In order to make sure the PLLs don’t unlock at some future time, the VCOs should be calibrated during initialization using the most accurate mode and should enable temperature compensation, both of which are used in the FDD mode.  Thus, the AD9361 would be initialized as if for FDD mode.  At the end of initialization, the ENSM would be moved to TDD mode and the VCO calibration would be disabled by setting bit D0 of 0x230 and 0x270 high.  This method would be shorter than the method above by the VCO calibration time.
  • Standard TDD mode/Dual Synth: In this case, the Dual Synth bit is set, enabling both PLLs and eliminating the PLL lock time (and the VCO calibration).  When switching to the Tx state, the Tx DAC must still power up and the flush times must still occur.  Similar to the method above, the AD9361 should be initialized as if for FDD mode.  The VCO calibration does not need to be disabled.
  • FDD Independent Mode: This configuration calibrates the AD9361 as if normal FDD mode would be used but allows the Rx and Tx paths to be enabled and disabled independently so there is infinite freedom in the timing of the Rx and Tx data paths.  The ENSM user guide describes this operation in more detail and the signals used.  The ENSM does not change state so the digital paths do not flush.  However, the Tx DAC still powers up and down along with the rest of the Tx signal path.
  • Standard FDD mode enables both LOs both data paths.  Since the Tx path is always on, LO leakage can couple back into the receiver through an external switch or duplexer which can degrade performance.  This mode would only be used if none of the ENSM TDD modes would work and if there was not sufficient flexibility in the baseband processor control signals to use the FDD Independent mode.
  • Share
  • History
  • More
  • Cancel
Comments
Anonymous
  • sripad
    sripad
    •  Analog Employees 
    over 2 years ago in reply to cliffz

    Yes your understanding is correct.

    • Cancel
    • Up 0 Down
    • Reply
    • More
    • Cancel
  • cliffz
    cliffz over 2 years ago

    I have an additional question about FDD Independent mode: as it says "However, the Tx DAC still powers up and down along with the rest of the Tx signal path". Does this mean it will still respect DAC power up time of 18us when moving to TX state? is this similar to Standard TDD mode/Dual Synth? 

     

    • Cancel
    • Up 0 Down
    • Reply
    • More
    • Cancel
Related
 
社交网络
快速链接
  • 关于ADI
  • Partners
  • 模拟对话
  • 职业
  • 联系我们
  • 投资信息
  • 新闻中心
  • 质量和可靠性
  • 办事处与代理商
  • Analog Garage
语言
  • English
  • 简体中文
  • 日本語
  • Руccкий
电子快讯

欲获得最新ADI产品、设计工具、培训与活动的相关新闻与文章,请从我们的在线快讯中选出您感兴趣的产品类别,每月或每季度都会发送至您的收件箱。

订阅
Switch to mobile view
Analog Logo
© 1995 - 2021 Analog Devices, Inc. All Rights Reserved 沪ICP备09046653号-1
  • ©
  • 1995 - 2021 Analog Devices, Inc. All Rights Reserved
  • 沪ICP备09046653号-1
  • 网站地图
  • 隐私和保密政策
  • 隐私设置
  • 使用条款
 
Social
Quick Links
  • About ADI
  • Partners
  • Analog Dialogue
  • Careers
  • Contact us
  • Investor Relations
  • News Room
  • Quality & Reliability
  • Sales & Distribution
  • Analog Garage
Languages
  • English
  • 简体中文
  • 日本語
  • Руccкий
Newsletters

Interested in the latest news and articles about ADI products, design tools, training and events? Choose from one of our 12 newsletters that match your product area of interest, delivered monthly or quarterly to your inbox.

Sign Up
Switch to mobile view
Analog Logo
© 1995 - 2021 Analog Devices, Inc. All Rights Reserved 沪ICP备09046653号-1
  • ©
  • 1995 - 2021 Analog Devices, Inc. All Rights Reserved
  • 沪ICP备09046653号-1
  • Sitemap
  • Privacy & Security
  • Privacy Settings
  • Terms of use
EngineerZone Uses cookies to ensure you get the best experience in our community. For more information on cookies, please read our Privacy & Security Statement.