AD936x devices have configurable Rx digital data path rates that are a subject to maximum ratings that vary based on the location of a digital block in the data path and the decimation rates available.
Rx data path below shows maximum data rates along the data path. Please do not exceed below specified rates for the blocks shown.
Timing design was closed at a maximum rate of 61.44 Msps regardless of any other conditions. It’s not an I/O limitation; it’s a limitation of each signal path. AD9361 and AD9364 are the same in this regard. 61.44 Msps is the max rate.
Interface timing is guaranteed up to 61.44 Msps and not recommended to use beyond this.
Yes it is not validated and not recommended.
We have gone through both the posts. It is understood that the chip can support interface sampling rates up to 122.88 Msps and also that, due to digital signal processing limitation in the Rx path, the maximum sampling rate is 64Msps. However, as per the info given in the beginning of this post, individual blocks in the Rx signal chain have different data rates as indicated in the block diagram. Hence we feel if we bypass RFIR block shown in the block diagram above, the maximum sampling rate should be 122.88Msps. From your reply above it is understood that you have not validated this. Is this correct?
No. Interface is validated for 61.44Msps.
please check below posts
AD9361 Maximum data rate, 122.88 or 61.44 MSPS?
https://ez.analog.com/message/246844?commentID=246844#comment-246844
Can i use the device at sampling rates of up to122Msps if i bypass the RFIR block .