AD936x transceiver digital driver output drive levels were chosen to minimize on chip noise due to digital waveform switching. The tradeoff associated with this approach is that the drivers cannot drive large capacitive loads. The maximum capacitive load specification is 3pF at 61.44MHz switching rate at 2.5V supply in CMOS mode. The drive level scales linearly with the digital switching rate, so for example at 30MHz switching rate the part can drive 6pF (load that is 2 times larger than at 60MHz).
If capacitive loading exceeds the specified maximum loading the recommendation would be to use a buffer.
At higher speeds we universally recommend using LVDS which is "quieter" than CMOS and can drive larger capacitive loads.
However, it comes at a cost of additional interface pins.
AD-FMCOMMS AD9361 and AD9364 evaluation platforms are designed to work in LVDS mode only. The board layout, connectors and FPGA inputs present a capacitive load that can be driven in LVDS mode, but not in CMOS mode. AD9361 and AD9364 digital interfaces support both modes of operation, LVDS and CMOS.
Would like to ask for clarification whether the 3 pF max load is trace capacitance or trace capacitance in addition to FPGA input capacitance? Also what if I am using 1.8 V supply rather than 2.5 V supply?