What can cause a drop of the bias voltage at the RX_EXT_LO_IN pin?

We have a design with two AD9361 and want to synchronize LOs by using an external LO. For this, I apply a sinus from a signal generator to the RX_EXT_LO_IN pins and set the appropriate registers. However, this doesn't work and while debugging we noticed that the bias voltage at our RX_EXT_LO_IN pins is only 0.03V instead of 0.5V as in the FMCOMM2 reference design. TX_EXT_LO_IN is grounded, but grounding the pin on the FMCOMM2 didn't cause a voltage drop. This voltage is generated chip internal, hence my question: What can cause a drop of the bias voltage at the RX_EXT_LO_IN pin?

Thanks!

- Thomas

  • 0
    •  Analog Employees 
    on Dec 7, 2016 2:34 PM

    A different question - why are we writing registers?

    EXT LO is part of the regular API.

    https://wiki.analog.com/resources/tools-software/linux-drivers/iio-transceiver/ad9361#external_lo_support

    -Michael

  • 0
    •  Analog Employees 
    on Dec 7, 2016 3:10 PM

    You need to use the latest kernel build from the xcomm_zynq branch.

    The additional clocks are only necessary if you want to control the external LO clock sources via the driver API.

    If you don't provide these in the devicetree the driver registers dummy clocks, and you can still use these API calls.

    # cat /sys/kernel/debug/clk/clk_summary
       clock                         enable_cnt  prepare_cnt        rate   accuracy   phase
    ----------------------------------------------------------------------------------------
     spi32766.0-tx_lo_dummy                   0            0  1225000000          0 0 
     spi32766.0-rx_lo_dummy                   0            0  1200000000          0 0 
     ad9364_ext_refclk                        4            4    40000000     200000 0 
        spi32766.0-bb_refclk                  1            1    40000000     200000 0 
           spi32766.0-bbpll_clk               1            1   983040000     200000 0 
              spi32766.0-adc_clk              1            1   245760000     200000 0 
                 spi32766.0-dac_clk           1            1   122880000     200000 0 
                    spi32766.0-t2_clk           1            1   122880000     200000 0 
                       spi32766.0-t1_clk           1            1    61440000     200000 0 
                          spi32766.0-clktf_clk           1            1    30720000     200000 0 
                             spi32766.0-tx_sampl_clk           1            1    30720000     200000 0 
                 spi32766.0-r2_clk            0            0   122880000     200000 0 
                    spi32766.0-r1_clk           0            0    61440000     200000 0 
                       spi32766.0-clkrf_clk           0            0    30720000     200000 0 
                          spi32766.0-rx_sampl_clk           0            0    30720000     200000 0 
        spi32766.0-rx_refclk                  1            1    80000000     200000 0 
           spi32766.0-rx_rfpll_int            1            1  1200000000     200000 0 
              spi32766.0-rx_rfpll             1            1  1200000000     200000 0 
        spi32766.0-tx_refclk                  1            1    80000000     200000 0 
           spi32766.0-tx_rfpll_int            1            1  1225000000     200000 0 
              spi32766.0-tx_rfpll             1            1  1225000000     200000 0 

    -Michael

  • 0
    •  Analog Employees 
    on Dec 7, 2016 3:28 PM

    not necessarily - what are you using at the moment?

    -Michael

  • On my board there is no AD7291 and iio:device0 is the correct device.

  • I don't have the out_altvoltage0_RX_LO_external/out_altvoltage1_TX_LO_external switches.

    Thanks a lot for providing the link. I figure, that I have to add clock-names “ext_tx_lo”/“ext_rx_lo” in the devicetree.

    The ad9361_clkin clock is currently described as

     ad9361_clkin: clock@0 {
       compatible = "fixed-clock";
       clock-frequency = <40000000>; // 40 MHz
       clock-output-names = "ad9361_ext_refclk";
    };

    How do I create non-fixed clocks ad9361_ext_tx_lo/ad9361_ext_rx_lo? Or, does it matter if the clock-frequency described in the devicetree does not match the clock-frequency that is actually provided?

    Thanks

    - Thomas