We have a design with two AD9361 and want to synchronize LOs by using an external LO. For this, I apply a sinus from a signal generator to the RX_EXT_LO_IN pins and set the appropriate registers. However, this doesn't work and while debugging we noticed that the bias voltage at our RX_EXT_LO_IN pins is only 0.03V instead of 0.5V as in the FMCOMM2 reference design. TX_EXT_LO_IN is grounded, but grounding the pin on the FMCOMM2 didn't cause a voltage drop. This voltage is generated chip internal, hence my question: What can cause a drop of the bias voltage at the RX_EXT_LO_IN pin?
What you are seeing could be due to damage to the chip or internal configuration. Do you see this issue on more than one board?
Please double check your SPI writes against the SPI Write sequences below. Ideally you should be using ADI provided drivers for device configuration.
The register setting for RX Ext. LO:
SPIWrite 005,77 // Both TX and RX use LO signals coming from Ext. LO
SPIWrite 050,0F // Enable RX LOGEN but power down RX VCO
SPIWrite 057,0x // Enable both TX and RX Ext. LO (NOTE preserve D3:D0 if desired)
SPIWrite 261,30 // Power down RX LOGEN divider
The register setting for TX Ext. LO:
SPIWrite 051,0F // Enable TX LOGEN but power down TX VCO, plus TX VCO LDO, therefore
external supply is needed for TX Ext. LO; If using TX VCO LDO for TX Ext. LO, set Reg050 = 0Eh)
SPIWrite 2A1,F0 // Power Down TX LOGEN divider
When using TX/RX Ext. LO, the corresponding internal RF synthesizer should be powered down (0x015[6:5] = 2’b11).
i did these register configuration for tX_LO, i use internal VCL LDO when I went through the register map register 051 should be 1E to power down LO but when i do the signal disappears,
the problem im facing is that i can see a spike of internal LO on the power spectrum analyzer. and the signal dynamic range is lower compared to the time im using internal LO.
do you have any Idea how can I solve it??