Hi, we're working with a PicoZed SDR (using AD9361) and have tried to understand how the RSSI is accumulated and when it can be read by looking at the datasheet and searching this forum for similar references but we're still confused.
1. For a TDD application, we are using rssi-restart-mode 2 (restart RSSI algorithm when the AD9361 enters rx mode). If the rx signal is asserted at the beginning of the slot and cleared at the end of slot, is the RSSI wait value used by the AD9361 or does it use only the RSSI delay value at the beginning since there is only one receive packet each slot?
2. Can the user application read the RSSI anytime during that the AD9361 is accumulating the RSSI value and get a valid RSSI value? From the documentation, it would seem that the application should wait until the AD9361 has completed its accumulation, but I want to confirm.
3. If the user application waits until the end of the slot to read the RSSI, then the RSSI value remains in the register even if the accumulation stopped earlier as specified by the RSSI duration value, is that correct? For our configuration, the rx signal is not asserted again until the next slot, so we should be able to read the RSSI value later.
FYI, we can design the PL side to trigger interrupts for specific events during the slot to the PS side to allow our PS software driver to go read the RSSI value in real time.
1. If the RX signal is asserted for every slot then RSSI delay value is used at the beginning always.
2. Yes application should wait till the accumulation of samples equal to RSSI total measurement duration.
3. Yes your understanding is correct
Thank you for the quick response. As a follow-up I have a question about calibration to get accurate RSSI values. We're dealing with applications in the 400MHz range. According to the reference manual as well as the AD9361 device driver the lowest range to do the gain step calibration to obtain the 2 error tables used to obtain more accurate RSSI values is 600 to 1300 MHz. How would you do calibration for 400MHz? The AD9361 device driver just groups a LO frequency of 400MHz as part of that lowest range (out of 4 ranges) when picking picking the gain step register values during calibration.
Do you do the calibration with a 400MHz tone or a 600MHz tone (smallest in lowest range) or even another frequency in the 600-1300 range?
I have tried calibration of the various tones mentioned above and I haven't been able to yield accurate RSSI values as compared to those an RF analyzer is displaying
Do the calibration near to 800 MHz as the gain table used for lower frequency range will be 800 MHz gain table. Set the LO to 800 MHz and tone to 805 MHz.
Thank you @sripad for your answers. They helped confirm our understanding. I have a few further questions I want to ask. We're using the PicoZed SDR with FMC carrier card and for our purposes, we have the PL designed such that the AD9361 is run in FDD mode, using FDD Independent Control, to better control when to do transmits and receives. We're able to write SW on the PS side such that it synchronizes to the receives so that it reads the RSSI value in real-time; we set the RSSI select mode to 2 (starts when the RFIC enters Rx mode). However, upon further testing, we're seeing that perhaps the RSSI algorithm accumulator is not "restarting or resetting the accumulator" when we think it should, resulting in us collecting inaccurate values.
For RSSI select mode 2 operation and FDD independent mode, when is the accumulator cleared? Only when RxON transitions from off to on? Is the algorithm still running when transitioning to Rx OFF (RxON low)? When the algorithm stops, does the accumulator retain latent values?
What happens when there are back-to-back receives, does RxON have to go to off then on again?
FDD independent mode is like FDD mode with RX/TX on off control but it not actual TDD mode.
RSSI mode 2 will work when ENSM is in TDD mode and not in FDD mode, you need to select other mode accordingly