AD 9361 Fast Attack AGC Transition From State 2 to 3, and 3 to 5?

A few questions about how AD9361 Fast Attack AGC transits from State 2 to 3, then from State 3 to 5:

Q1) According to UG671, Fast Attack AGC locks the gain upon entering State 3. How does the AGC determine that it should exit State 2 and enter into State 3? Specifically, in State 2 the gain will be adjust to match the AGC Lock Level. How long does the AGC wait after gain adjustment before entering State 3?

Q2) In State 3, if there is no overload conditions, how long does the AGC wait before entering State 5?

  • 0
    •  Analog Employees 
    on Jan 30, 2017 2:03 PM over 4 years ago

    1. AGC waits in state 2 till the gain is below AGC Lock Level (Fast) and if Enable LMT Gain Incr for Lock Level bit of 0x111[D6] is enabled and gain increase is required then there is a maximum amount that it can increase, set by “AGC Max Increase” in 0x118. Once this is done it moves to State3, 

    2. In state 3 it waits for at least one dec power measurement and then move to state5

    In state 2 and state 3 the wait time is mostly affected by the dec power measurement duration set in 0x15C

  • 0
    •  Analog Employees 
    on Aug 2, 2018 3:43 PM over 2 years ago
    This question has been assumed as answered either offline via email or with a multi-part answer. This question has now been closed out. If you have an inquiry related to this topic please post a new question in the applicable product forum.

    Thank you,
    EZ Admin