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AD9364 TX/RX path latency

We have an application that is very sensitive to latency in both the TX and RX paths.

The AD9364 Reference Manual explains the latency due to the digital filters, but in addition to this latency, we are measuring an additional latency that is not explained in the data sheet or reference manual.

Our clock setup using the no-os drivers is as follows:
ad9361_set_trx_clock_chain: 960000000 480000000 240000000 120000000 60000000 60000000
ad9361_set_trx_clock_chain: 960000000 240000000 120000000 60000000 60000000 60000000

Looking at the AD9364 users guide "DIGITAL Rx BLOCK DELAY" it looks like I should be seeing a delay contribution from the digital filters of approx:
                  HB3           HB2           HB1   
RX path (2/240M) + (2/120M) + (7/60M) = 8.3ns + 16.6ns + 116ns = 140ns
TX path (2/120M) + (2/60M)  + 0             = 16.6ns + 33.8ns             =  50.4ns
 
= 190.4ns total delay for digital filters

I am using an ILA (logic analyzer) in our FPGA to capture the TX and RX data just before clocking in/out to the AD9364.  I am seeing a delay of approx. 800ns.

 

I know that the 190ns is only the digital filter delay.  Is there a description somewhere of what the source might be for the additional ~600ns delay I am measuring?

Most importantly for our application, is there anything that can be done to reduce the latency below the 800ns we are currently seeing?

 

Thank you for any assistance.

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  • Hope you understood why we take filter rates in RX, I can see that now you consider filter rates in latest calculation.

    But still you are using wrong filter orders

    If you compare from UG-570 

    Recalculated 

      TX Interpolation Filter order Delay RX Decimation Filter order Delay
    Data rate 6.00E+07       6.00E+07      
    FIR 6.00E+07 1 0 0.00E+00 6.00E+07 1 0 0.00E+00
    HB1 6.00E+07 1 0 0.00E+00 1.20E+08 2 14 5.83E-08
    HB2 1.20E+08 2 6 2.50E-08 2.40E+08 2 6 1.25E-08
    HB3 1.20E+08 1 2 8.33E-09 4.80E+08 2 4 4.17E-09
                     
          TX Delay 3.3333E-08     RX delay 7.5E-08
    Total 1.08E-07

    It is around 108 ns.

    Is it possible for you to generate a pulsed signal in TX and capture same in RX after loop back and check the delay.

    Also share ILA capture for same.

    RX Filter setting and group delay

    TX Filter setting and group delay

    Even when we don't enable internal FIR the tool calculates group delay expecting user will implement FIR in BB and gives a FIR with few taps.

    If we add delay with 19 taps for FIR the delay for TX is around 192 ns and RX is 233 ns and it matches with the simulation results.

    Please try same using pulsed input and verify.

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  • Hope you understood why we take filter rates in RX, I can see that now you consider filter rates in latest calculation.

    But still you are using wrong filter orders

    If you compare from UG-570 

    Recalculated 

      TX Interpolation Filter order Delay RX Decimation Filter order Delay
    Data rate 6.00E+07       6.00E+07      
    FIR 6.00E+07 1 0 0.00E+00 6.00E+07 1 0 0.00E+00
    HB1 6.00E+07 1 0 0.00E+00 1.20E+08 2 14 5.83E-08
    HB2 1.20E+08 2 6 2.50E-08 2.40E+08 2 6 1.25E-08
    HB3 1.20E+08 1 2 8.33E-09 4.80E+08 2 4 4.17E-09
                     
          TX Delay 3.3333E-08     RX delay 7.5E-08
    Total 1.08E-07

    It is around 108 ns.

    Is it possible for you to generate a pulsed signal in TX and capture same in RX after loop back and check the delay.

    Also share ILA capture for same.

    RX Filter setting and group delay

    TX Filter setting and group delay

    Even when we don't enable internal FIR the tool calculates group delay expecting user will implement FIR in BB and gives a FIR with few taps.

    If we add delay with 19 taps for FIR the delay for TX is around 192 ns and RX is 233 ns and it matches with the simulation results.

    Please try same using pulsed input and verify.

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