We have an application that is very sensitive to latency in both the TX and RX paths.
The AD9364 Reference Manual explains the latency due to the digital filters, but in addition to this latency, we are measuring an additional latency that is not explained in the data sheet or reference manual.
Our clock setup using the no-os drivers is as follows:
ad9361_set_trx_clock_chain: 960000000 480000000 240000000 120000000 60000000 60000000
ad9361_set_trx_clock_chain: 960000000 240000000 120000000 60000000 60000000 60000000
Looking at the AD9364 users guide "DIGITAL Rx BLOCK DELAY" it looks like I should be seeing a delay contribution from the digital filters of approx:
HB3 HB2 HB1
RX path (2/240M) + (2/120M) + (7/60M) = 8.3ns + 16.6ns + 116ns = 140ns
TX path (2/120M) + (2/60M) + 0 = 16.6ns + 33.8ns = 50.4ns
= 190.4ns total delay for digital filters
I am using an ILA (logic analyzer) in our FPGA to capture the TX and RX data just before clocking in/out to the AD9364. I am seeing a delay of approx. 800ns.
I know that the 190ns is only the digital filter delay. Is there a description somewhere of what the source might be for the additional ~600ns delay I am measuring?
Most importantly for our application, is there anything that can be done to reduce the latency below the 800ns we are currently seeing?
Thank you for any assistance.