DATA_CLK is the output clk of RX FIR(RX_SAMPLE_CLK) ?

 

    When I use AD9364, the clk of ADC is  245760000 Hz. I set the register of 0x00A is 0xfa , I get the 3.8MHz clk from the pin of clkout. So I consider my config is right. 

    Then I set the register of 0x003 is 0x5e . From this config, I consider Data_clk must 15.36MHz, But I real test from oscilloscope, the clk of Data_clk is 31MHz. Why the Data_clk is not same with my expectation? The Data_clk is Rx_sample_clk?

   the attachment is my wave of oscilloscope.

attachments.zip
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  • +1
    •  Analog Employees 
    on Mar 5, 2018 6:40 AM

    You can't set the TX FIR decimation in the rates array init structure (rx_path_clock_frequencies, tx_path_clock_frequencies).

    In addition RX and TX sample clock must always be equal!

    Please use:

    ad9361_set_tx_fir_config(ad9361_phy, tx_fir_config);

    ad9361_set_rx_fir_config(ad9361_phy, rx_fir_config)

    ad9361_set_trx_fir_en_dis(ad9361_phy, 1);

    or use:

    ad9361_trx_load_enable_fir()

    In 1Rx1Tx mode using LVDS full duplex mode. The DATA_CLK clock is twice the baseband rate. 

    -Michael

  • Hello,

    I have a similar question. I am using LTE20 from AD9361 filter wizard and it works fine in 2TX by 2Rx mode (but in 1Tx1Rx at the Rx I get half of the signal I sent), but when I set up the driver for 1Tx 1Rx mode (both set to 1 indicating channel 1) I get the error: 

    Error with InitRadio640
    Error code 0xC0850022: AD9361 module - No solution could be found for the digital calibration

    I followed the process of the code I am using and from what I read this error appears at the calibration of the digital communication between the FPGA and the Radio640 (where Radio630 is the AD8361 plus some other stuff).

    So at this step, I am still using the LTE20 filter at both sides ( 30.72 MHz sampling rate):

    TX 3 GAIN -6 INT 2
    RX 3 GAIN -6 DEC 2
    RTX 983040000 245760000 245760000 122880000 61440000 30720000
    RRX 983040000 491520000 245760000 122880000 61440000 30720000
    BWTX 19365438
    BWRX 19365514

    with 

    two_rx_two_tx_mode_enable=0
    one_rx_one_tx_mode_use_rx_num=1
    one_rx_one_tx_mode_use_tx_num=1     ( setup as default parameters and also values taken from initialisation file to make sure this are input correctly every time) 

    What is your suggestion, how should debug this and fix the sampling rates (if this is the problem..), or the problem comes from somewhere else? Please let me know, I`ve been stuck on this for a while now. Thank you very much!

    Kind regards,

    George

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  • Hello,

    I have a similar question. I am using LTE20 from AD9361 filter wizard and it works fine in 2TX by 2Rx mode (but in 1Tx1Rx at the Rx I get half of the signal I sent), but when I set up the driver for 1Tx 1Rx mode (both set to 1 indicating channel 1) I get the error: 

    Error with InitRadio640
    Error code 0xC0850022: AD9361 module - No solution could be found for the digital calibration

    I followed the process of the code I am using and from what I read this error appears at the calibration of the digital communication between the FPGA and the Radio640 (where Radio630 is the AD8361 plus some other stuff).

    So at this step, I am still using the LTE20 filter at both sides ( 30.72 MHz sampling rate):

    TX 3 GAIN -6 INT 2
    RX 3 GAIN -6 DEC 2
    RTX 983040000 245760000 245760000 122880000 61440000 30720000
    RRX 983040000 491520000 245760000 122880000 61440000 30720000
    BWTX 19365438
    BWRX 19365514

    with 

    two_rx_two_tx_mode_enable=0
    one_rx_one_tx_mode_use_rx_num=1
    one_rx_one_tx_mode_use_tx_num=1     ( setup as default parameters and also values taken from initialisation file to make sure this are input correctly every time) 

    What is your suggestion, how should debug this and fix the sampling rates (if this is the problem..), or the problem comes from somewhere else? Please let me know, I`ve been stuck on this for a while now. Thank you very much!

    Kind regards,

    George

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