AD9361 design questions

We've got a couple of AD9361 PCB design questions that I figured would be best to bundle into a single post.

1) What is the maximum TX and RX data trace slack, assuming the maximum sample rate of 61.44Msps? In other words, what is the maximum length/TOF delay between A_P1_D0, A_P1_D1, A_P1_D2, etc...

2) What is the recommended bypass capacitor configuration? Right now we're using the ADP1755 with a configuration of ferrite -> 0.1uF -> small power plane (to minimize parasitic inductance) for all 1.3V digital and analog supplies. Does adding a 10uF capacitor or doing 0.1uF -> ferrite -> 0.1uF -> power plane significantly improve the 9361's performance?

3) What is the nominal peak-to-peak voltage for the SYNC_IN signal? We couldn't much information on this in the wiki or datasheet.

Thanks!

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  • 0
    •  Analog Employees 
    on Mar 26, 2018 11:06 AM over 2 years ago

    1. From UG 570:

    Transmit data is driven on P0_D[11:6] by the BBP such that the setup and hold times between FB_CLK and P0_D[11:6] allow the AD9361 to use FB_CLK to capture the data. Receive data is driven on P0_D[5:0] by the AD9361 such that the setup and hold times between DATA_CLK and P0_D[5:0] arriving at the BBP enable the BBP to use DATA_CLK to capture the data

    Each data line has to meet the individual timing requirement as specified . 

    Please refer below link for interface tuning. 

    Digital Interface Timing Verification [Analog Devices Wiki] 

    2. 0402 components will have lower ESR and can be placed closer to the pins. You can use any package for decaps . Care must be taken in their placement.

    3. yes it is 1.3V.

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  • 0
    •  Analog Employees 
    on Mar 26, 2018 11:06 AM over 2 years ago

    1. From UG 570:

    Transmit data is driven on P0_D[11:6] by the BBP such that the setup and hold times between FB_CLK and P0_D[11:6] allow the AD9361 to use FB_CLK to capture the data. Receive data is driven on P0_D[5:0] by the AD9361 such that the setup and hold times between DATA_CLK and P0_D[5:0] arriving at the BBP enable the BBP to use DATA_CLK to capture the data

    Each data line has to meet the individual timing requirement as specified . 

    Please refer below link for interface tuning. 

    Digital Interface Timing Verification [Analog Devices Wiki] 

    2. 0402 components will have lower ESR and can be placed closer to the pins. You can use any package for decaps . Care must be taken in their placement.

    3. yes it is 1.3V.

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