AD9361 design questions

We've got a couple of AD9361 PCB design questions that I figured would be best to bundle into a single post.

1) What is the maximum TX and RX data trace slack, assuming the maximum sample rate of 61.44Msps? In other words, what is the maximum length/TOF delay between A_P1_D0, A_P1_D1, A_P1_D2, etc...

2) What is the recommended bypass capacitor configuration? Right now we're using the ADP1755 with a configuration of ferrite -> 0.1uF -> small power plane (to minimize parasitic inductance) for all 1.3V digital and analog supplies. Does adding a 10uF capacitor or doing 0.1uF -> ferrite -> 0.1uF -> power plane significantly improve the 9361's performance?

3) What is the nominal peak-to-peak voltage for the SYNC_IN signal? We couldn't much information on this in the wiki or datasheet.

Thanks!

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    •  Analog Employees 
    on Mar 23, 2018 5:32 PM

    1. Please refer UG-570 for data timing constrains . (table 49, CMOS and table 51 for LVDS)

    2. You can refer , Evaluation board reference schematics for reference. Additional filtering requirements will be benificial if your board has other digital parts other than AD9361.

    3. Will get back on the level for sync_in. It should be same as reference clock.  Sync_in details are available in UG-570 section under BASEBAND SYNCHRONIZATION. 

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  • 0
    •  Analog Employees 
    on Mar 23, 2018 5:32 PM

    1. Please refer UG-570 for data timing constrains . (table 49, CMOS and table 51 for LVDS)

    2. You can refer , Evaluation board reference schematics for reference. Additional filtering requirements will be benificial if your board has other digital parts other than AD9361.

    3. Will get back on the level for sync_in. It should be same as reference clock.  Sync_in details are available in UG-570 section under BASEBAND SYNCHRONIZATION. 

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