AD9361 FAST AGC

Hi,

 

I am using fast AGC in a TDD burst system.

The convergence time of the AGC is too slow for my signal which is an OFDM signal with GI of 128 (convergence takes about 250-300 samples). How can I make it much faster?

 

Another problem is that if I increase the signal power up to about -50dBm then the RSSI (probably due to the AGC) jumps suddenly up to about -35dBm and the signal gets disturbed in such a way that errors start on the link. What can be the problem?

 

Thanks,

Y

  • 0
    •  Analog Employees 
    on Sep 29, 2014 5:42 PM over 6 years ago

    Which standard are you working with?

    Do you have a timing specification you are trying to achieve for AGC convergence? How much of an improvement are you looking for?

    What hardware are you using and how are you configuring the part?

  • We are using an LTE like system

    The guard interval time is about 5.7usec, I would like convergence within 2-3usec.

    We are using our own HW.

    The System is using the No-OS driver and is configuring it the following:

        phy->pdata->gain_ctrl.adc_large_overload_exceed_counter = 10;

        phy->pdata->gain_ctrl.adc_large_overload_inc_steps = 5;

        phy->pdata->gain_ctrl.adc_lmt_small_overload_prevent_gain_inc = FALSE;

        phy->pdata->gain_ctrl.adc_small_overload_exceed_counter = 10;

        phy->pdata->gain_ctrl.adc_small_overload_inc_steps = 4;

        phy->pdata->gain_ctrl.dig_gain_step_size = 4;

        phy->pdata->gain_ctrl.dig_saturation_exceed_counter = 3;

        phy->pdata->gain_ctrl.gain_update_interval_us = 1000;

        phy->pdata->gain_ctrl.immed_gain_change_if_large_adc_overload = FALSE;

        phy->pdata->gain_ctrl.immed_gain_change_if_large_lmt_overload = FALSE;

        phy->pdata->gain_ctrl.agc_inner_thresh_high = 10;

        phy->pdata->gain_ctrl.agc_inner_thresh_high_dec_steps = 1;

        phy->pdata->gain_ctrl.agc_inner_thresh_low = 12;

        phy->pdata->gain_ctrl.agc_inner_thresh_low_inc_steps = 1;

        phy->pdata->gain_ctrl.lmt_overload_large_exceed_counter = 10;

        phy->pdata->gain_ctrl.lmt_overload_large_inc_steps = 2;

        phy->pdata->gain_ctrl.lmt_overload_small_exceed_counter = 10;

        phy->pdata->gain_ctrl.agc_outer_thresh_high = 5;

        phy->pdata->gain_ctrl.agc_outer_thresh_high_dec_steps = 2;

        phy->pdata->gain_ctrl.agc_outer_thresh_low = 18;

        phy->pdata->gain_ctrl.agc_outer_thresh_low_inc_steps = 2;

        phy->pdata->gain_ctrl.agc_attack_delay_extra_margin_us = 2;

        phy->pdata->gain_ctrl.sync_for_gain_counter_en = FALSE;

    The system is a TDD one, where we use the chip in TDD mode (and not FDD).

    Thanks,

  • 0
    •  Analog Employees 
    on Oct 6, 2014 11:53 PM over 6 years ago

    It will be hard to meet 2-3us convergence or lock time.

    I would recommend using Fast Lock AGC algorithm. The function calls you provided appear to be for slow AGC.

    The way to come close to meeting your specification is to run the part at maximum output data rate which in turn will maximize ClkRF at 122.88MHz. AGC is clocked by ClkRF and the faster ClkRF the faster the AGC operates.

  • 0
    •  Analog Employees 
    on Aug 2, 2018 2:46 PM over 2 years ago
    This question has been assumed as answered either offline via email or with a multi-part answer. This question has now been closed out. If you have an inquiry related to this topic please post a new question in the applicable product forum.

    Thank you,
    EZ Admin