What sampling rate and data path to prefer for AD9361?

The filter wizard and driver have slightly different algorithms to calculate the sample rate. However, you can modify the filters used in the filter wizard to match the driver manually. The filter wizard is meant for more analysis, while the sample rate attribute will just set something in range.

For best performance, the rule of thumb is to run the ADC as fast as possible and decimate as much as possible. This will provide the best ENOB and noise-shaping performance.

-Travis

Thank you for your reply,

What if my product requires moderate power consumption? I'm afraid running the ADC as fast as possible will raise my power consumption, no?

Let's put it this way: if I want to save power, for let's say 10MHz BW, what minimum factor shall I apply to get my ADC sampling, in order to have still a decent RF performance? At what point the device will be critically limited?

Moving to AD9361 specific support. I’m not sure if we have data on this tradeoff and will likely be application specific. You will likely have to test different configurations based on your waveform and modem performance.

-Travis

OK.

I started with a 3x factor (ADC at 30MSPS), and performance is questionnable. With useful signal at -10dBFs, some spurious are appearring at -20dBc on the spectrum from time to time. Then, with 6x factor, it seems a bit better. To conclude, this behaviour is not so surprizing for such a "slow" ADC?

I would say more at low decimation. The AD936x family has a sigma-delta ADC architecture, so it's designed to be followed by decimation to grow bits and remove passband skirts.

-Travis