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ADRV9364-Z7020 IQ mismatch

Category: Hardware
Product Number: ADRV9364-Z702


we wrote a python script using PyADI library, using the original FPGA design supplied by ADI, in which we transmit CW from the TX using DDS, and recive it in RX via leakage. than we cpature samples from the RX and take it for analysis in Matlab.

the issue is that we see image rejections around 30-40dB, which is not enough for us.

is there any IQ calibration (TX and RX) mechanism inside the AD9361 chip itself? 

or any more high level procedure that can be activated via the PyADI  AD9364 object?