We have our own board with zynq-ultrascale+ and ad9361 chip,
in the PCB we routed the sync_in pin of the chip to UFL connector.
we routed in the HDL the ADC clock form the chip to one of the pins on the board.
Now we are trying to sync two chips on different boards (one chip on each board),
on an oscilloscope we can see the ADC clock of each board,
we run MCS procedure in the no-OS code,
for the slave commands we implement a UART com. between the two processors (PS).
and for the sync_in pulse we tried, a pulse from the master board, & external pulse synchronized to the sys clock.
we can see on the scope that the two ADC clock are changing the phase,
but the doesn't get to be align. in addition they even doesn't have a constant delay (which is good cause it point on trace mismatch).
every time we rum the MSC we get different phase between the two clocks.