Post Go back to editing

CMOS interface

Category: Datasheet/Specs
Product Number: AD9361
Software Version: Null

From the words in the first picture(UG-570, page100), we can see that every rising edge of the RX-FRAME comes with a new frame, but in the picture below(Figure71,page101), you can see that frame in the red box is coming with a falling edge of a RX-FRAME, could you help me to check which one is right? The words or the picture.

  • Since its DDR , so the capture will be at both negedge and posedge of the DATA_CLK 

    From UG:

    The BBP uses this master clock(DATA_CLK) as the timing reference for the interface data transfers and for the baseband data processing. DATA_CLK provides source-synchronous timing with dual edge capture (DDR) or single rising-edge capture (SDR) data transfer during receive operation.

    FB_CLK also provides source synchronous timing with dual edge capture (DDR) or single rising-edge capture (SDR) for D[11:0] data signals during Tx bursts (both P0 and P1)