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AD9364 - Tx/Rx LO Frequency Change Settling Time

Category: Software

Table 1. and p. 12 of the AD9364 reference manual both explain that when changing the Tx/Rx LO frequency more than 100MHz, a calibration is required. If I understand this correctly, this means that a calibration is required when changing to a frequency 100MHz away from the last calibrated value.

However, if hopping between LO frequencies that are all within 100MHz of the last calibrated LO frequency, a calibration shouldn't be necessary. Is this correct? What problems will occur if a calibration is not run?

Aside from the SPI register reads/writes necessary to set the Tx/Rx LO, how much time is there for the LO to settle? Or in other words, exactly how much time is there between the last SPI write to set the RF LO, and when the LO has settled on the desired frequency? (assuming there is no calibration).

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  • , I've moved this thread to the appropriate Design Support forum, the questions are specifically about ad9364 design/specs.

  • However, if hopping between LO frequencies that are all within 100MHz of the last calibrated LO frequency, a calibration shouldn't be necessary. Is this correct? What problems will occur if a calibration is not run?

    Yes, calibration is not necessary if the LO frequency is within 100 MHz. If you don't do calibrations if LO/Carrier frequency is more than 100 MHz it will have an impact on DC offset and quadrature correction.

    Aside from the SPI register reads/writes necessary to set the Tx/Rx LO, how much time is there for the LO to settle? Or in other words, exactly how much time is there between the last SPI write to set the RF LO, and when the LO has settled on the desired frequency? (assuming there is no calibration).

    Use Fast lock profiles to achieve faster switching time, for more information refer "Fast Lock Profile" section in the AD9364 user guide. 

  • In this case, when using a fastlock profile, after the SPI write for selecting the profile and setting the transfer bit, how long does the fastlock profile take to load, and for the LO to settle in analog?

    Also, by what mechanism does the AD9364 transfer fastlock profile information to/from the BBP? The number of profiles I would like to use is several times beyond the 8 in on-chip memory.

  • In this case, when using a fastlock profile, after the SPI write for selecting the profile and setting the transfer bit, how long does the fastlock profile take to load, and for the LO to settle in analog?

    LO settling time is in order of micro sec approx 20-50, what is your requirement for LO settling time? This depends on the SPI clock and synthesizer settings.

    Also, by what mechanism does the AD9364 transfer fastlock profile information to/from the BBP? The number of profiles I would like to use is several times beyond the 8 in on-chip memory.

    how many profiles do you want to use? which mode are you planning to operate TDD or FDD?

    A profile can be recalled by either issuing a single SPI command that contains the desired profile number and transfer bit, or alternatively, a profile can be selected in hardware by setting the appropriate code on control input pins. At that time, all the on-chip stored profile information is transferred into the synthesizer registers, the synthesizer is immediately configured, and it is released to lock as quickly as the loop BW allows. 

    Refer user guide "Fast lock profile" section to understand more.

  • I will be operating in TDD mode and would like to have at least 81 profiles. I want to be able to hop frequencies rapidly across a specific frequency band.

    I would like to be able to change both the Tx & Rx LO frequencies in under 100us total. This includes all of the SPI transactions necessary, as well as the Tx/Rx LO settling.

  • It is possible to save only a maximum of 8 profiles inside the chip memory. You need to save the remaining profiles inside your BBP memory. There are API's for doing so. Refer to the below link:

     fastlock profile with more than 8 profile saving. 

    Each frequency hop takes around 15-20usec. So hopping 81 profiles within 100usec might not be possible. 

  • I should clarify, I want to be able to switch from one LO freq to another LO freq on both the Tx&Rx LO within 100us. For example:

    State 1: Tx&Rx LO = Freq A

    State 2: Tx&Rx LO = Freq B

    The switch from A to B for both the Tx&Rx LO's needs to occurr within 100us. I don't need to hop between all 81 frequencies within 100us.

    In the reference manual, it states that after choosing a fastlock profile, the LO "is released to lock as quickly as the loop BW allows." Is this loop BW time the 15-20us that you're referring to? Or is there additional settling time? I'm assuming the SPI messages and memory transfer time required to select and load the fastlock profile for the freq. hop take additional time.

  • It is possible to switch the frequencies of Tx&Rx LO from one state to another within 100usec including settling time.

  • Just so I understand better,

    In the reference manual, it states that after choosing a fastlock profile, the LO "is released to lock as quickly as the loop BW allows." Earlier you mentioned that each freq. hop takes around 15-20us. Is this loop BW time the 15-20us that you're referring to? Or is there additional settling time that must be considered as well?

  • 15-20 usec is the time to attain PLL lock time, on top of this you need to consider SPI time between BBP and AD9361, and also in this case need to consider the time of profile extraction from BBP as well since a large niumber of profiles are stored in BBP memory.