I am working with a Zynq 7000 and AD9361 using ADI IIO OSC, how can I verify the clock for the ADC and how verify the clock for the FPGA?
how can I verify the clock for the ADC and how verify the clock for the FPGA?
Depending on the input data rate to the FIR, the rates for all the filters and the ADC/DAC clock rates will be set accordingly.
You can use the matlab based filter wizard tool to get an understanding on how the path rates for the digital datapath are set.
Download it from the below link:
Are you talking about the DATA_CLK that goes from the AD9361 to the FPGA?