Use of ad9361 below 70 MHz

Are you using Linux or NO-OS drivers for configuring the chip?

The chip will not work for frequencies below 70MHz. Best approach is to use down conversion mixers for going below 70MHz.

Hey, first of all thanks for the response.

We use linux drivers for configuring the chip.

We searched online for a solution and we found the register map and saw the following:

which seems like these are registers that change the vco frequency, and with setting the divider to 128, we could reach 46.875 MHZ lo freq.

The question we have is, how do you set the vco frequency through these 2 registers. For example if I want 6GHZ, what do we write to them.

Thanks a lot

darroz said:

which seems like these are registers that change the vco frequency, and with setting the divider to 128, we could reach 46.875 MHZ lo freq.

we don't recommend operating the AD9361 device <70 MHz and performance is optimized from 70M-6GHz if you intend to use the part below 70 MHz you need to verify the performance before using it.

darroz said:

The question we have is, how do you set the vco frequency through these 2 registers. For example if I want 6GHZ, what do we write to them.

are you using no-Os drivers? or register read and write. if you have no-os drivers it calculates and writes register values based on the channel frequency.

For example, if you want to operate at 6GHz, follow the below steps

1. Identify VCO frequency with the formula mentioned below, in this case, the divider value is '0', and VCO freq (Frfpll is = 12GHz)

2. Identify the Integer and fractional values from the below formula.

Note: Need to use the final reference frequency (after clock divider) for the below calculations.

Hey,

Thanks for your response.

We followed your instructions and are stuck at the last level, since we do not know how to get the final reference frequency. We use an internal clock and not an external and we would like to know in which register we could read the internal clock frequency.

Thanks a lot

The reference clock frequency is from External or DCXO, May I know what is your configuration or arch of the clock section of AD9361. 

The final reference clock frequency can be calculated with the following steps.

The reference clock frequency must be between 5MHz and 320MHz
and can be scaled by 1x, ½ x, ¼ x, and 2x using BBPLL, Rx and Tx reference dividers (registers 0x045, 0x2AB and 0x2AC
respectively). The valid frequency range for the PLL phase detectors is 10MHz to 80MHz and the scaled frequency of the reference clock input.
The clock must be within this range. The recommended range for the RF PLLs for optimum phase noise is 40MHz – 80MHz.