AD9361 SUGGESTION

Hello everyone,

I request you to please give some suggestion for the queries that are mentioned below.

  1. RF4 freq is up converted with independent LO programmable through SPI from AD9361 to arrive at 70.7 MHz freq.
  2. The RF2 is down converted to arrive at 90 MHz
  3. RF3 has no conversion of frequency being 75 MHz
  4. All 3 different frequencies are combined by a combiner and fed as input to RX2 of AD9361.
  5. In case of RF1 the frequency is directly fed in to RX1 of AD9361.
  6. Common crystal oscillator will be in use for all 3 mixing stages. Whereas the control is through SPI independently.
  7. In case of RF1 we do the down conversion to get the output as 70 MHz and is fed to AD9361.
  8. TX1 / TX2 - Confirm the possibility of utilizing the Internally generated freq from the AD9361 signal generator and will be used to generate the self-test function for all 4 Rx channels. Modulated freq for each channel will be generated for the purpose of self-test for the respective channels from TX1.
 
DSP : 
  1. Whether with RX1 and RX2 the IF values mentioned in the block diagram, can we recover the modulation. 

Thanks in advance.



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[edited by: Zakir Hussain at 5:48 AM (GMT -5) on 9 Nov 2021]
  • AD9361 is of direct conversion architecture and simply downconverts or upconverts the input signal. There is no modulation/demodulation/ other signal processing implemented in this chip. You need to do the DSP in your FPGA.

    In case of three frequency input to the RX2 port, you can configure the RX LO such that the three signals which will fall on different IF frequency at the RX output,  will remain within the RF BW that is set. then you can use NCO inside your FPGA to further downconvert the three IF to the DC and demodulate each.